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commit f15d60906974891ab9fce2724a1b2cdcc467b9e4 Author: raiden00pl <[email protected]> AuthorDate: Sun Aug 16 11:13:37 2026 +0200 arch/arm/stm32h5: use common Kconfig symbols The headers test CONFIG_STM32H5_* names that no Kconfig defines (the STM32H5xXXX families, FLASHEN, OTFDEC1EN, DCACHE, STM32H2X/H3X/H7X), so those branches are dead code. Use the common CONFIG_STM32_* symbols. Fix what this exposes: derive the SRAM2/SRAM3 bases from the family SRAM sizes, since the boot ECC init would otherwise write past the end of RAM on smaller parts, correct the H52x/H53x SPI count to SPI1-4 and drop the STM32_STM32H5X3XX select, which names no symbol. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/include/stm32h5/chip.h | 22 +++++----- arch/arm/include/stm32h5/irq.h | 4 +- arch/arm/include/stm32h5/stm32h5xx_irq.h | 22 +++++----- arch/arm/src/stm32h5/Kconfig | 3 +- arch/arm/src/stm32h5/hardware/stm32_gpdma.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_gpio.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_i2c.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_memorymap.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_pwr.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_rcc.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_sbs.h | 6 +-- arch/arm/src/stm32h5/hardware/stm32_uart.h | 4 +- arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h | 2 +- arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h | 28 ++++++------- .../src/stm32h5/hardware/stm32h5xxx_memorymap.h | 11 +++-- arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h | 4 +- arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h | 2 +- arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h | 2 +- arch/arm/src/stm32h5/stm32_adc.h | 8 ++-- arch/arm/src/stm32h5/stm32_ethernet.c | 8 ++-- arch/arm/src/stm32h5/stm32_i2c.c | 2 +- arch/arm/src/stm32h5/stm32_pwm.c | 48 +++++++++++----------- arch/arm/src/stm32h5/stm32_pwm.h | 8 ++-- arch/arm/src/stm32h5/stm32_serial.c | 28 ++++++------- arch/arm/src/stm32h5/stm32_spi.c | 2 +- arch/arm/src/stm32h5/stm32_start.c | 2 +- arch/arm/src/stm32h5/stm32_tim.c | 44 ++++++++++---------- arch/arm/src/stm32h5/stm32_uart.h | 42 +++++++++---------- arch/arm/src/stm32h5/stm32_usbdrdhost.c | 14 +++---- arch/arm/src/stm32h5/stm32h5xx_rcc.c | 18 ++++---- 30 files changed, 179 insertions(+), 177 deletions(-) diff --git a/arch/arm/include/stm32h5/chip.h b/arch/arm/include/stm32h5/chip.h index ad98276331c..6170e394acd 100644 --- a/arch/arm/include/stm32h5/chip.h +++ b/arch/arm/include/stm32h5/chip.h @@ -33,12 +33,12 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */ # define STM32_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */ -#elif defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) +# define STM32_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ # define STM32_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */ #else @@ -54,10 +54,10 @@ #define STM32_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */ #define STM32_NRNG (1) /* Random number generator (RNG) */ -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_NUART (6) /* UART 4-5, 7-8, 9, 12 */ # define STM32_NUSART (5) /* USART 1-3, 6, 10-11 */ -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define STM32_NUART (2) /* UART 4-5 */ # define STM32_NUSART (4) /* USART 1-3, 6*/ #endif @@ -66,11 +66,11 @@ #define STM32_QSPI (0) /* No QuadSPI1 */ #define STM32_OCTOSPI (1) /* OCTOSPI1*/ -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_NSPI (6) /* SPI1-SPI6 */ # define STM32_NI2C (4) /* I2C1-4 */ -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32_NSPI (3) /* SPI1-SPI3 */ +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) +# define STM32_NSPI (4) /* SPI1-SPI4 */ # define STM32_NI2C (3) /* I2C1-3 */ #endif @@ -80,9 +80,9 @@ #define STM32_NCAN (2) /* CAN1 */ #define STM32_NSAI (2) /* SAI1-2 */ -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_NSDMMC (2) /* SDMMC interface */ -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define STM32_NSDMMC (1) /* SDMMC interface */ #endif diff --git a/arch/arm/include/stm32h5/irq.h b/arch/arm/include/stm32h5/irq.h index aec185b9f9e..68c53b2704e 100644 --- a/arch/arm/include/stm32h5/irq.h +++ b/arch/arm/include/stm32h5/irq.h @@ -65,8 +65,8 @@ #define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include <arch/stm32h5/stm32h5xx_irq.h> #else # error "Unsupported STM32 H5 chip" diff --git a/arch/arm/include/stm32h5/stm32h5xx_irq.h b/arch/arm/include/stm32h5/stm32h5xx_irq.h index 5550c7e5b99..b6582c3ec07 100644 --- a/arch/arm/include/stm32h5/stm32h5xx_irq.h +++ b/arch/arm/include/stm32h5/stm32h5xx_irq.h @@ -119,7 +119,7 @@ # define STM32_IRQ_ADC2 (STM32_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */ # define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */ # define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */ -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 72) /* 72: TIM16 global interrupt */ # define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 73) /* 73: TIM17 global interrupt */ #endif @@ -132,12 +132,12 @@ # define STM32_IRQ_I2C3_EV (STM32_IRQ_FIRST + 80) /* 80: I2C3_EV global interrupt */ # define STM32_IRQ_I2C3_ER (STM32_IRQ_FIRST + 81) /* 81: I2C3_ER global interrupt */ # define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 82) /* 82: SPI4 global interrupt */ -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_SPI5 (STM32_IRQ_FIRST + 83) /* 83: SPI5 global interrupt */ # define STM32_IRQ_SPI6 (STM32_IRQ_FIRST + 84) /* 84: SPI6 global interrupt */ #endif # define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 85) /* 85: USART6 global interrupt */ -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_USART10 (STM32_IRQ_FIRST + 86) /* 86: USART10 global interrupt */ # define STM32_IRQ_USART11 (STM32_IRQ_FIRST + 87) /* 87: USART11 global interrupt */ # define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 88) /* 88: SAI1 global interrupt */ @@ -151,7 +151,7 @@ # define STM32_IRQ_GPDMA2_CH5 (STM32_IRQ_FIRST + 95) /* 95: GPDMA2_CH5 global interrupt */ # define STM32_IRQ_GPDMA2_CH6 (STM32_IRQ_FIRST + 96) /* 96: GPDMA2_CH6 global interrupt */ # define STM32_IRQ_GPDMA2_CH7 (STM32_IRQ_FIRST + 97) /* 97: GPDMA2_CH7 global interrupt */ -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_UART7 (STM32_IRQ_FIRST + 98) /* 98: UART7 global interrupt */ # define STM32_IRQ_UART8 (STM32_IRQ_FIRST + 99) /* 99: UART8 global interrupt */ # define STM32_IRQ_UART9 (STM32_IRQ_FIRST + 100) /* 100: UART9 global interrupt */ @@ -161,14 +161,14 @@ # define STM32_IRQ_FPU (STM32_IRQ_FIRST + 103) /* 103: FPU global interrupt */ # define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 104) /* 104: ICACHE global interrupt */ # define STM32_IRQ_DCACHE (STM32_IRQ_FIRST + 105) /* 105: DCACHE global interrupt */ -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_ETH (STM32_IRQ_FIRST + 106) /* 106: ETH global interrupt */ # define STM32_IRQ_ETH_WKUP (STM32_IRQ_FIRST + 107) /* 107: ETH_WKUP global interrupt */ #endif # define STM32_IRQ_DCMI_PSSI (STM32_IRQ_FIRST + 108) /* 108: DCMI PSSI global interrupt */ # define STM32_IRQ_FDCAN2_IT0 (STM32_IRQ_FIRST + 109) /* 109: FDCAN2_IT0 global interrupt */ # define STM32_IRQ_FDCAN2_IT1 (STM32_IRQ_FIRST + 110) /* 110: FDCAN2_IT1 global interrupt */ -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 111) /* 111: CORDIC global interrupt */ # define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 112) /* 112: FMAC global interrupt */ #endif @@ -180,13 +180,13 @@ # define STM32_IRQ_PKA (STM32_IRQ_FIRST + 118) /* 118: PKA global interrupt */ # define STM32_IRQ_CEC (STM32_IRQ_FIRST + 119) /* 119: CEC global interrupt */ # define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 120) /* 120: TIM12 global interrupt */ -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 121) /* 121: TIM13 global interrupt */ # define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 122) /* 122: TIM14 global interrupt */ #endif # define STM32_IRQ_I3C1_EV (STM32_IRQ_FIRST + 123) /* 123: I3C1_EV global interrupt */ # define STM32_IRQ_I3C1_ER (STM32_IRQ_FIRST + 124) /* 124: I3C1_ER global interrupt */ -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_I2C4_EV (STM32_IRQ_FIRST + 125) /* 125: I2C4_EV global interrupt */ # define STM32_IRQ_I2C4_ER (STM32_IRQ_FIRST + 126) /* 126: I2C4_ER global interrupt */ # define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 127) /* 127: LPTIM3 global interrupt */ @@ -194,14 +194,14 @@ # define STM32_IRQ_LPTIM5 (STM32_IRQ_FIRST + 129) /* 129: LPTIM5 global interrupt */ # define STM32_IRQ_LPTIM6 (STM32_IRQ_FIRST + 130) /* 130: LPTIM6 global interrupt */ #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define STM32_IRQ_I3C2_EV (STM32_IRQ_FIRST + 131) /* 131: I3C2_EV global interrupt */ # define STM32_IRQ_I3C2_ER (STM32_IRQ_FIRST + 132) /* 132: I3C2_ER global interrupt */ #endif -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_NEXTINTS 131 -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define STM32_IRQ_NEXTINTS 133 #endif diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index cdddeae5840..c4c8c3bdbff 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -40,11 +40,10 @@ config ARCH_CHIP_STM32H563ZI select STM32_STM32H5XXXX select STM32_STM32H56XXX select STM32_STM32H563XX - select STM32_STM32H5X3XX select STM32_FLASH_CONFIG_I select STM32H5_IO_CONFIG_Z ---help--- - STM32 H5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM + STM32 H5 Cortex M33, 2 Mb FLASH, 640 Kb SRAM endchoice # STM32 H5 Chip Selection diff --git a/arch/arm/src/stm32h5/hardware/stm32_gpdma.h b/arch/arm/src/stm32h5/hardware/stm32_gpdma.h index cdee82e895b..997c2180495 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_gpdma.h +++ b/arch/arm/src/stm32h5/hardware/stm32_gpdma.h @@ -30,7 +30,7 @@ #include <nuttx/config.h> #include "chip.h" -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "stm32h56x_dmasigmap.h" #else # error "Unsupported STM32 H5 DMA map" diff --git a/arch/arm/src/stm32h5/hardware/stm32_gpio.h b/arch/arm/src/stm32h5/hardware/stm32_gpio.h index 8d271424a1d..8ff9b98ab84 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32h5/hardware/stm32_gpio.h @@ -30,8 +30,8 @@ #include <nuttx/config.h> #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_gpio.h" #else # error "Unsupported STM32 H5 PWR" diff --git a/arch/arm/src/stm32h5/hardware/stm32_i2c.h b/arch/arm/src/stm32h5/hardware/stm32_i2c.h index ce97ded64f2..d564ba5f1ec 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32h5/hardware/stm32_i2c.h @@ -30,8 +30,8 @@ #include <nuttx/config.h> #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_i2c.h" #else # error "Unsupported STM32 H5 I2C" diff --git a/arch/arm/src/stm32h5/hardware/stm32_memorymap.h b/arch/arm/src/stm32h5/hardware/stm32_memorymap.h index 72f4dec37be..ff9b80be0fe 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32h5/hardware/stm32_memorymap.h @@ -30,8 +30,8 @@ #include <nuttx/config.h> #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_memorymap.h" #else # error "Unsupported STM32 H5 memory map" diff --git a/arch/arm/src/stm32h5/hardware/stm32_pwr.h b/arch/arm/src/stm32h5/hardware/stm32_pwr.h index 269f5a3d9df..24cddd0b400 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32h5/hardware/stm32_pwr.h @@ -30,8 +30,8 @@ #include <nuttx/config.h> #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_pwr.h" #else # error "Unsupported STM32 H5 PWR" diff --git a/arch/arm/src/stm32h5/hardware/stm32_rcc.h b/arch/arm/src/stm32h5/hardware/stm32_rcc.h index cf8cc1fd0bd..ecfa04f7d52 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h5/hardware/stm32_rcc.h @@ -30,8 +30,8 @@ #include <nuttx/config.h> #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_rcc.h" #else # error "Unsupported STM32 H5 rcc" diff --git a/arch/arm/src/stm32h5/hardware/stm32_sbs.h b/arch/arm/src/stm32h5/hardware/stm32_sbs.h index 5d3655aa7ba..06c8a9fb6cf 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_sbs.h +++ b/arch/arm/src/stm32h5/hardware/stm32_sbs.h @@ -30,10 +30,10 @@ #include <nuttx/config.h> #include "chip.h" -#if !defined(CONFIG_STM32H5_STM32H52XXX) && \ - !defined(CONFIG_STM32H5_STM32H53XXX) && \ +#if !defined(CONFIG_STM32_STM32H52XXX) && \ + !defined(CONFIG_STM32_STM32H53XXX) && \ !defined(CONFIG_STM32_STM32H56XXX) && \ - !defined(CONFIG_STM32H5_STM32H57XXX) + !defined(CONFIG_STM32_STM32H57XXX) # warning "SBS not verified on STM32H50x variants." #endif diff --git a/arch/arm/src/stm32h5/hardware/stm32_uart.h b/arch/arm/src/stm32h5/hardware/stm32_uart.h index 96e87f40144..1b974188d5d 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_uart.h +++ b/arch/arm/src/stm32h5/hardware/stm32_uart.h @@ -30,8 +30,8 @@ #include <nuttx/config.h> #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_uart.h" #else # error "Unsupported STM32 H5 uart" diff --git a/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h b/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h index 3d709daa0c7..57284c4e07c 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h +++ b/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h @@ -30,7 +30,7 @@ #include <nuttx/config.h> #if defined(CONFIG_STM32_STM32H563XX) || \ - defined(CONFIG_STM32H5_STM32H562XX) + defined(CONFIG_STM32_STM32H562XX) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h index 8aed24fcab6..78fffb5e695 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h @@ -481,12 +481,12 @@ #define FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT (0) #define FLASH_SECWM1R_CUR_SECWM1_END_SHIFT (16) -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_SECWM1R_CUR_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_CUR_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_SECWM1R_CUR_SECWM1_STRT_MASK (0x1f << FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_CUR_SECWM1_END_MASK (0x1f << FLASH_SECWM1R_CUR_SECWM1_END_SHIFT) #endif @@ -496,12 +496,12 @@ #define FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT (0) #define FLASH_SECWM1R_PRG_SECWM1_END_SHIFT (16) -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_SECWM1R_PRG_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_PRG_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_SECWM1R_PRG_SECWM1_STRT_MASK (0x1f << FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_PRG_SECWM1_END_MASK (0x1f << FLASH_SECWM1R_PRG_SECWM1_END_SHIFT) #endif @@ -527,12 +527,12 @@ #define FLASH_HDP1R_CUR_HDP1_STRT_SHIFT (0) #define FLASH_HDP1R_CUR_HDP1_END_SHIFT (0) -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP1R_CUR_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_CUR_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP1R_CUR_HDP1_STRT_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_CUR_HDP1_END_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif @@ -542,12 +542,12 @@ #define FLASH_HDP1R_PRG_HDP1_STRT_SHIFT (0) #define FLASH_HDP1R_PRG_HDP1_END_SHIFT (0) -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP1R_PRG_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_PRG_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP1R_PRG_HDP1_STRT_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_PRG_HDP1_END_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif @@ -587,12 +587,12 @@ #define FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT (0) #define FLASH_SECWM2R_PRG_SECWM2_END_SHIFT (16) -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_SECWM2R_PRG_SECWM2_STRT_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT) # define FLASH_SECWM2R_PRG_SECWM2_END_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_SECWM2R_PRG_SECWM2_STRT_MASK (0x1f << FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT) # define FLASH_SECWM2R_PRG_SECWM2_END_MASK (0x1f << FLASH_SECWM2R_PRG_SECWM2_END_SHIFT) #endif @@ -618,12 +618,12 @@ #define FLASH_HDP2R_CUR_HDP2_STRT_SHIFT (0) #define FLASH_HDP2R_CUR_HDP2_END_SHIFT (0) -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP2R_CUR_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_CUR_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP2R_CUR_HDP2_STRT_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_CUR_HDP2_END_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif @@ -633,12 +633,12 @@ #define FLASH_HDP2R_PRG_HDP2_STRT_SHIFT (0) #define FLASH_HDP2R_PRG_HDP2_END_SHIFT (0) -#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP2R_PRG_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_PRG_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP2R_PRG_HDP2_STRT_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_PRG_HDP2_END_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h index b235d903a67..ea0bc9e05ff 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h @@ -49,10 +49,13 @@ #define STM32_FLASH_BANK1 0x08000000 /* 0x08000000-0x080fffff: Bank 1 (562/563/573xx devices) */ #define STM32_FLASH_BANK2 0x08100000 /* 0x08100000-0x081fffff: Bank 2 (562/563/573xx devices) */ #define STM32_FLASH_BASE STM32_FLASH_BANK1 -#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ -#define STM32_SRAM2_BASE 0x20040000 /* 0x20040000-0x2004ffff: 64k SRAM2 */ -#define STM32_SRAM3_BASE 0x20050000 /* 0x20050000-0x2008ffff: 320k SRAM3 */ - /* 0x20090000-0x2009ffff: Reserved for ECC */ +/* SRAM1, SRAM2 and SRAM3 are contiguous on all STM32H5 parts, but their + * sizes are family-dependent (STM32_SRAMx_SIZE comes from chip.h). + */ + +#define STM32_SRAM1_BASE 0x20000000 +#define STM32_SRAM2_BASE (STM32_SRAM1_BASE + STM32_SRAM1_SIZE) +#define STM32_SRAM3_BASE (STM32_SRAM2_BASE + STM32_SRAM2_SIZE) /* System Memory Addresses **************************************************/ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h index 1329727d65d..8c065d39c4b 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h @@ -93,13 +93,13 @@ #define PWR_PMCR_ETHERNETSO (1 << 16) /* Ethernet RAM shut-off in Stop Mode */ #define PWR_PMCR_SRAM3SO (1 << 23) /* AHB SRAM3 shut-off in Stop mode */ -#if defined(CONFIG_STM32H5_STM32H56X) || defined(CONFIG_STM32H5_STM32H7X) +#if defined(CONFIG_STM32_STM32H56X) || defined(CONFIG_STM32_STM32H7X) #define PWR_PMCR_SRAM2_16SO (1 << 24) /* AHB SRAM3 16-Kbyte shut-off in Stop mode **/ #define PWR_PMCR_SRAM2_48SO (1 << 25) /* AHB SRAM2 48-Kbyte shut-off in Stop mode **/ #define PWR_PMCR_SRAM1SO (1 << 26) /* AHB SRAM1 shut-off in Stop mode * */ -#elif defined(CONFIG_STM32H5_STM32H2X) || defined(CONFIG_STM32H5_STM32H3X) +#elif defined(CONFIG_STM32_STM32H2X) || defined(CONFIG_STM32_STM32H3X) #define PWR_PMCR_SRAM2_16LSO (1 << 24) /* AHB SRAM3 16-Kbyte Low shut-off in Stop mode **/ #define PWR_PMCR_SRAM2_16HSO (1 << 25) /* AHB SRAM3 16-Kbyte High shut-off in Stop mode **/ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h index eafd85eb2e3..3383507d502 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h @@ -1242,5 +1242,5 @@ #define RCC_PRIVCFGR_SPRIV (1 << 0) /* Secure functions privilege configuration */ #define RCC_PRIVCFGR_NSPRIV (1 << 1) /* Non-secure functions privilege configuration */ -#endif /* CONFIG_STM32H5_STM32H562XX */ +#endif /* CONFIG_STM32_STM32H5XXXX */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_RCC_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h index 8c6abc212aa..14418be6737 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h @@ -489,5 +489,5 @@ #define SPI_I2SCFGR_ODD (1 << 24) /* Bit 24: Odd Factor for the Prescaler */ #define SPI_I2SCFGR_MCKOE (1 << 25) /* Bit 24: Master Clock Output Enable */ -#endif /* CONFIG_STM32H5_STM32H5XXX */ +#endif /* CONFIG_STM32_STM32H5XXX */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_SPI_H */ diff --git a/arch/arm/src/stm32h5/stm32_adc.h b/arch/arm/src/stm32h5/stm32_adc.h index fe614304886..dcbf844f9d5 100644 --- a/arch/arm/src/stm32h5/stm32_adc.h +++ b/arch/arm/src/stm32h5/stm32_adc.h @@ -41,8 +41,8 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32H5_TIMn is defined then - * CONFIG_STM32H5_TIMn_ADC must also be defined to indicate that timer "n" + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" * is intended to be used for that purpose. */ @@ -119,12 +119,12 @@ #endif #undef ADC_HAVE_WDG2 -#if defined(CONFIG_STM32H5_ADC1_WDG2) || defined(CONFIG_STM32H5_ADC2_WDG2) +#if defined(CONFIG_STM32_ADC1_WDG2) || defined(CONFIG_STM32_ADC2_WDG2) # define ADC_HAVE_WDG2 1 #endif #undef ADC_HAVE_WDG3 -#if defined(CONFIG_STM32H5_ADC1_WDG3) || defined(CONFIG_STM32H5_ADC2_WDG3) +#if defined(CONFIG_STM32_ADC1_WDG3) || defined(CONFIG_STM32_ADC2_WDG3) # define ADC_HAVE_WDG3 1 #endif diff --git a/arch/arm/src/stm32h5/stm32_ethernet.c b/arch/arm/src/stm32h5/stm32_ethernet.c index c8853e1aebb..0ef2f2eb4b9 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.c +++ b/arch/arm/src/stm32h5/stm32_ethernet.c @@ -93,9 +93,9 @@ /* Select work queue */ -# if defined(CONFIG_STM32H5_ETHMAC_HPWORK) +# if defined(CONFIG_STM32_ETHMAC_HPWORK) # define ETHWORK HPWORK -# elif defined(CONFIG_STM32H5_ETHMAC_LPWORK) +# elif defined(CONFIG_STM32_ETHMAC_LPWORK) # define ETHWORK LPWORK # else # define ETHWORK LPWORK @@ -182,8 +182,8 @@ #define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 15) & ~15) -#ifdef CONFIG_STM32H5_ETH_BUFSIZE -# define ETH_BUFSIZE CONFIG_STM32H5_ETH_BUFSIZE +#ifdef CONFIG_STM32_ETH_BUFSIZE +# define ETH_BUFSIZE CONFIG_STM32_ETH_BUFSIZE #else # define ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE #endif diff --git a/arch/arm/src/stm32h5/stm32_i2c.c b/arch/arm/src/stm32h5/stm32_i2c.c index 9af288dd911..7a12a60a683 100644 --- a/arch/arm/src/stm32h5/stm32_i2c.c +++ b/arch/arm/src/stm32h5/stm32_i2c.c @@ -158,7 +158,7 @@ * * One of: * - * CONFIG_STM32H5_STM32H5XXXXX + * CONFIG_STM32_STM32H5XXXXX * * and one or more interfaces: * diff --git a/arch/arm/src/stm32h5/stm32_pwm.c b/arch/arm/src/stm32h5/stm32_pwm.c index 5ace24e0cca..43848bae35b 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.c +++ b/arch/arm/src/stm32h5/stm32_pwm.c @@ -175,10 +175,10 @@ /* Break support */ -#if defined(CONFIG_STM32H5_TIM1_BREAK1) || defined(CONFIG_STM32H5_TIM1_BREAK2) || \ - defined(CONFIG_STM32H5_TIM8_BREAK1) || defined(CONFIG_STM32H5_TIM8_BREAK2) || \ - defined(CONFIG_STM32H5_TIM15_BREAK1) || defined(CONFIG_STM32H5_TIM16_BREAK1) || \ - defined(CONFIG_STM32H5_TIM17_BREAK1) +#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ + defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) || \ + defined(CONFIG_STM32_TIM15_BREAK1) || defined(CONFIG_STM32_TIM16_BREAK1) || \ + defined(CONFIG_STM32_TIM17_BREAK1) # defined HAVE_BREAK #endif @@ -390,14 +390,14 @@ static struct stm32_pwmchan_s g_pwm1channels[] = #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM1_BREAK1 +#ifdef CONFIG_STM32_TIM1_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM1_BRK1POL, + .pol1 = CONFIG_STM32_TIM1_BRK1POL, #endif -#ifdef CONFIG_STM32H5_TIM1_BREAK2 +#ifdef CONFIG_STM32_TIM1_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32H5_TIM1_BRK2POL, - .flt2 = CONFIG_STM32H5_TIM1_BRK2FLT, + .pol2 = CONFIG_STM32_TIM1_BRK2POL, + .flt2 = CONFIG_STM32_TIM1_BRK2FLT, #endif }, #endif @@ -935,14 +935,14 @@ static struct stm32_pwmchan_s g_pwm8channels[] = #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM8_BREAK1 +#ifdef CONFIG_STM32_TIM8_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM8_BRK1POL, + .pol1 = CONFIG_STM32_TIM8_BRK1POL, #endif -#ifdef CONFIG_STM32H5_TIM8_BREAK2 +#ifdef CONFIG_STM32_TIM8_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32H5_TIM8_BRK2POL, - .flt2 = CONFIG_STM32H5_TIM8_BRK2FLT, + .pol2 = CONFIG_STM32_TIM8_BRK2POL, + .flt2 = CONFIG_STM32_TIM8_BRK2FLT, #endif }, #endif @@ -1258,9 +1258,9 @@ static struct stm32_pwmchan_s g_pwm15channels[] = #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM15_BREAK1 +#ifdef CONFIG_STM32_TIM15_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM15_BRK1POL, + .pol1 = CONFIG_STM32_TIM15_BRK1POL, #endif /* No BREAK2 */ }, @@ -1340,9 +1340,9 @@ static struct stm32_pwmchan_s g_pwm16channels[] = #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM16_BREAK1 +#ifdef CONFIG_STM32_TIM16_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM16_BRK1POL, + .pol1 = CONFIG_STM32_TIM16_BRK1POL, #endif /* No BREAK2 */ }, @@ -1360,8 +1360,8 @@ static struct stm32_pwmchan_s g_pwm16channels[] = .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM16_CH1NPOL, - .idle = CONFIG_STM32H5_TIM16_CH1NIDLE, + .pol = CONFIG_STM32_TIM16_CH1NPOL, + .idle = CONFIG_STM32_TIM16_CH1NIDLE, .pincfg = PWM_TIM16_CH2CFG, } #endif @@ -1406,9 +1406,9 @@ static struct stm32_pwmchan_s g_pwm17channels[] = #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM17_BREAK1 +#ifdef CONFIG_STM32_TIM17_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM17_BRK1POL, + .pol1 = CONFIG_STM32_TIM17_BRK1POL, #endif /* No BREAK2 */ }, @@ -1426,8 +1426,8 @@ static struct stm32_pwmchan_s g_pwm17channels[] = .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM17_CH1NPOL, - .idle = CONFIG_STM32H5_TIM17_CH1NIDLE, + .pol = CONFIG_STM32_TIM17_CH1NPOL, + .idle = CONFIG_STM32_TIM17_CH1NIDLE, .pincfg = PWM_TIM17_CH2CFG, } #endif diff --git a/arch/arm/src/stm32h5/stm32_pwm.h b/arch/arm/src/stm32h5/stm32_pwm.h index bfbe59529fa..138d2ad573b 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.h +++ b/arch/arm/src/stm32h5/stm32_pwm.h @@ -52,7 +52,7 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. - * If CONFIG_STM32H5_TIMn is defined then the CONFIG_STM32H5_TIMn_PWM must + * If CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must * also be defined to indicate that timer "n" is intended to be used for * pulsed output signal generation. */ @@ -98,8 +98,8 @@ * pulses */ -#undef CONFIG_STM32H5_TIM6_PWM -#undef CONFIG_STM32H5_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ @@ -326,7 +326,7 @@ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32H5_TIMx_CHANNEL - Specifies the timer output channel + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel * {1,..,4} * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. * In the case where there are multiple pin selections, the correct diff --git a/arch/arm/src/stm32h5/stm32_serial.c b/arch/arm/src/stm32h5/stm32_serial.c index c7de84c7054..590facc5144 100644 --- a/arch/arm/src/stm32h5/stm32_serial.c +++ b/arch/arm/src/stm32h5/stm32_serial.c @@ -403,7 +403,7 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER static char g_usart10rxbuffer[CONFIG_USART10_RXBUFSIZE]; static char g_usart10txbuffer[CONFIG_USART10_TXBUFSIZE]; # ifdef CONFIG_USART10_RXDMA @@ -411,7 +411,7 @@ static char g_usart10rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER static char g_usart11rxbuffer[CONFIG_USART11_RXBUFSIZE]; static char g_usart11txbuffer[CONFIG_USART11_TXBUFSIZE]; # ifdef CONFIG_USART11_RXDMA @@ -1120,7 +1120,7 @@ static struct stm32_serial_s g_uart8priv = /* This describes the state of the STM32 UART9 port. */ -#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifdef CONFIG_STM32_UART9_SERIALDRIVER static struct stm32_serial_s g_uart9priv = { .dev = @@ -1197,7 +1197,7 @@ static struct stm32_serial_s g_uart9priv = /* This describes the state of the STM32 USART10 port. */ -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER static struct stm32_serial_s g_usart10priv = { .dev = @@ -1274,7 +1274,7 @@ static struct stm32_serial_s g_usart10priv = /* This describes the state of the STM32 USART11 port. */ -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER static struct stm32_serial_s g_usart11priv = { .dev = @@ -1351,7 +1351,7 @@ static struct stm32_serial_s g_usart11priv = /* This describes the state of the STM32 UART12 port. */ -#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER static struct stm32_serial_s g_uart12priv = { .dev = @@ -1458,16 +1458,16 @@ static struct stm32_serial_s * const #ifdef CONFIG_STM32_UART8_SERIALDRIVER [8] = &g_uart8priv, #endif -#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifdef CONFIG_STM32_UART9_SERIALDRIVER [9] = &g_uart9priv, #endif -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER [10] = &g_usart10priv, #endif -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER [11] = &g_usart11priv, #endif -#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER [12] = &g_uart12priv, #endif }; @@ -2105,26 +2105,26 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifdef CONFIG_STM32_UART9_SERIALDRIVER case STM32_UART9_BASE: rcc_en = RCC_APB1HENR_UART9EN; regaddr = STM32_RCC_APB1HENR; break; #endif -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER case STM32_USART10_BASE: rcc_en = RCC_APB1LENR_USART10EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER case STM32_USART11_BASE: rcc_en = RCC_APB1LENR_USART11EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER case STM32_UART12_BASE: rcc_en = RCC_APB1HENR_UART12EN; regaddr = STM32_RCC_APB1HENR; diff --git a/arch/arm/src/stm32h5/stm32_spi.c b/arch/arm/src/stm32h5/stm32_spi.c index fd0b621d7e9..42ce61211f7 100644 --- a/arch/arm/src/stm32h5/stm32_spi.c +++ b/arch/arm/src/stm32h5/stm32_spi.c @@ -76,7 +76,7 @@ #include "stm32_dma.h" #endif -#if defined(CONFIG_STM32H5_STM32H50XXX) +#if defined(CONFIG_STM32_STM32H50XXX) # define SPI_MAX_KER_CK 250000000 #else # define SPI_MAX_KER_CK 125000000 diff --git a/arch/arm/src/stm32h5/stm32_start.c b/arch/arm/src/stm32h5/stm32_start.c index f87eeb75b6e..62acdd78f69 100644 --- a/arch/arm/src/stm32h5/stm32_start.c +++ b/arch/arm/src/stm32h5/stm32_start.c @@ -190,7 +190,7 @@ void __start(void) } #endif -#ifdef CONFIG_STM32H5_SRAM3_INIT +#ifdef CONFIG_STM32_SRAM3_INIT for (dest = (uint32_t *)SRAM3_START; dest < (uint32_t *)SRAM3_END; ) { *dest++ = 0; diff --git a/arch/arm/src/stm32h5/stm32_tim.c b/arch/arm/src/stm32h5/stm32_tim.c index 56f70ffdb93..2be01522413 100644 --- a/arch/arm/src/stm32h5/stm32_tim.c +++ b/arch/arm/src/stm32h5/stm32_tim.c @@ -53,20 +53,20 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32H5_TIMn is defined then the CONFIG_STM32H5_TIMn_PWM may + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may * also be defined to indicate that the timer is intended to be used for * pulsed output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32H5_TIMn is - * defined then CONFIG_STM32H5_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32H5_TIMn is defined - * then CONFIG_STM32H5_TIMn_DAC may also be defined to indicate that + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that * timer "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32H5_TIMn is defined then - * CONFIG_STM32H5_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. @@ -97,13 +97,13 @@ # undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32H5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32H5_TIM6_QE) +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) # undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32H5_TIM7_PWM) || defined (CONFIG_STM32H5_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32H5_TIM7_QE) +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) # undef CONFIG_STM32_TIM7 #endif @@ -112,33 +112,33 @@ # undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32H5_TIM12_ADC) || \ - defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32H5_TIM12_QE) +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) # undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32H5_TIM13_ADC) || \ - defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32H5_TIM13_QE) +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) # undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32H5_TIM14_ADC) || \ - defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32H5_TIM14_QE) +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) # undef CONFIG_STM32_TIM14 #endif #if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32H5_TIM15_DAC) || defined(CONFIG_STM32H5_TIM15_QE) + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) # undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32H5_TIM16_ADC) || \ - defined(CONFIG_STM32H5_TIM16_DAC) || defined(CONFIG_STM32H5_TIM16_QE) +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) # undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32H5_TIM17_ADC) || \ - defined(CONFIG_STM32H5_TIM17_DAC) || defined(CONFIG_STM32H5_TIM17_QE) +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) # undef CONFIG_STM32_TIM17 #endif diff --git a/arch/arm/src/stm32h5/stm32_uart.h b/arch/arm/src/stm32h5/stm32_uart.h index 2a9756b89b1..f6530cf94bb 100644 --- a/arch/arm/src/stm32h5/stm32_uart.h +++ b/arch/arm/src/stm32h5/stm32_uart.h @@ -125,20 +125,20 @@ # undef CONFIG_STM32_UART8_1WIREDRIVER #endif #if !defined(CONFIG_STM32_UART9) -# undef CONFIG_STM32H5_UART9_SERIALDRIVER -# undef CONFIG_STM32H5_UART9_1WIREDRIVER +# undef CONFIG_STM32_UART9_SERIALDRIVER +# undef CONFIG_STM32_UART9_1WIREDRIVER #endif #if !defined(CONFIG_STM32_USART10) -# undef CONFIG_STM32H5_USART10_SERIALDRIVER -# undef CONFIG_STM32H5_USART10_1WIREDRIVER +# undef CONFIG_STM32_USART10_SERIALDRIVER +# undef CONFIG_STM32_USART10_1WIREDRIVER #endif #if !defined(CONFIG_STM32_USART11) -# undef CONFIG_STM32H5_USART11_SERIALDRIVER -# undef CONFIG_STM32H5_USART11_1WIREDRIVER +# undef CONFIG_STM32_USART11_SERIALDRIVER +# undef CONFIG_STM32_USART11_1WIREDRIVER #endif #if !defined(CONFIG_STM32_UART12) -# undef CONFIG_STM32H5_UART12_SERIALDRIVER -# undef CONFIG_STM32H5_UART12_1WIREDRIVER +# undef CONFIG_STM32_UART12_SERIALDRIVER +# undef CONFIG_STM32_UART12_1WIREDRIVER #endif /* Is there a USART enabled? */ @@ -149,7 +149,7 @@ defined(CONFIG_STM32_USART6) || defined(CONFIG_STM32_UART7) || \ defined(CONFIG_STM32_UART8) || defined(CONFIG_STM32_UART9) || \ defined(CONFIG_STM32_USART10) || defined(CONFIG_STM32_USART11) || \ - defined(CONFIG_STM32H5_USART12) + defined(CONFIG_STM32_USART12) # define HAVE_UART 1 #endif @@ -290,7 +290,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 9 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART9_SERIALDRIVER) +#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART9_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -305,7 +305,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 10 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART10_SERIALDRIVER) +#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART10_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -320,7 +320,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 11 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART11_SERIALDRIVER) +#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART11_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -335,7 +335,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 12 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART12_SERIALDRIVER) +#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART12_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -417,19 +417,19 @@ # undef CONFIG_UART8_RXDMA #endif -#ifndef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifndef CONFIG_STM32_UART9_SERIALDRIVER # undef CONFIG_UART9_RXDMA #endif -#ifndef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifndef CONFIG_STM32_USART10_SERIALDRIVER # undef CONFIG_USART10_RXDMA #endif -#ifndef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifndef CONFIG_STM32_USART11_SERIALDRIVER # undef CONFIG_USART11_RXDMA #endif -#ifndef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifndef CONFIG_STM32_UART12_SERIALDRIVER # undef CONFIG_UART12_RXDMA #endif @@ -498,13 +498,13 @@ # undef SERIAL_HAVE_ONLY_DMA #elif defined(CONFIG_STM32_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART9_SERIALDRIVER) && !defined(CONFIG_UART9_RXDMA) +#elif defined(CONFIG_STM32_UART9_SERIALDRIVER) && !defined(CONFIG_UART9_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART10_SERIALDRIVER) && !defined(CONFIG_USART10_RXDMA) +#elif defined(CONFIG_STM32_USART10_SERIALDRIVER) && !defined(CONFIG_USART10_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART11_SERIALDRIVER) && !defined(CONFIG_USART11_RXDMA) +#elif defined(CONFIG_STM32_USART11_SERIALDRIVER) && !defined(CONFIG_USART11_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART12_SERIALDRIVER) && !defined(CONFIG_UART12_RXDMA) +#elif defined(CONFIG_STM32_UART12_SERIALDRIVER) && !defined(CONFIG_UART12_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.c b/arch/arm/src/stm32h5/stm32_usbdrdhost.c index e368b914107..1333ef56ae5 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.c +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.c @@ -78,8 +78,8 @@ # define CONFIG_STM32_USBDRD_DESCSIZE 128 #endif -#ifndef CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT -# define CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT 5000 +#ifndef CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT +# define CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT 5000 #endif /* Hardware definitions */ @@ -1225,7 +1225,7 @@ static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, } stm32_transfer_start(priv, ep0->outndx); - return stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + return stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); } /**************************************************************************** @@ -1257,7 +1257,7 @@ static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, } stm32_transfer_start(priv, ep0->outndx); - return stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + return stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); } /**************************************************************************** @@ -1289,7 +1289,7 @@ static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, } stm32_transfer_start(priv, ep0->inndx); - return stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + return stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); } /**************************************************************************** @@ -1321,7 +1321,7 @@ static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, stm32_transfer_start(priv, chidx); - ret = stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + ret = stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); if (ret < 0) { return ret; @@ -1359,7 +1359,7 @@ static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, stm32_transfer_start(priv, chidx); - ret = stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + ret = stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); if (ret < 0) { return ret; diff --git a/arch/arm/src/stm32h5/stm32h5xx_rcc.c b/arch/arm/src/stm32h5/stm32h5xx_rcc.c index b730ce54bbe..07a60f5a68c 100644 --- a/arch/arm/src/stm32h5/stm32h5xx_rcc.c +++ b/arch/arm/src/stm32h5/stm32h5xx_rcc.c @@ -113,7 +113,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_GPDMA2EN; #endif -#ifdef CONFIG_STM32H5_FLASHEN +#ifdef CONFIG_STM32_FLASH /* Flash memory interface clock enable */ regval |= RCC_AHB1ENR_FLASHEN; @@ -157,18 +157,18 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_ETHRXEN; #endif -#ifdef CONFIG_STM32H5_TZSC1 +#ifdef CONFIG_STM32_TZSC1 regval |= RCC_AHB1ENR_TZSC1EN; #endif -#ifdef CONFIG_STM32H5_BKPRAM +#ifdef CONFIG_STM32_BKPRAM /* BKPRAM clock enable */ regval |= RCC_AHB1ENR_BKPRAMEN; #endif -#ifdef CONFIG_STM32H5_DCACHE +#ifdef CONFIG_STM32_DCACHE1 /* DCACHE clock enable */ regval |= RCC_AHB1ENR_DCACHEEN; @@ -314,7 +314,7 @@ static inline void rcc_enableahb4(void) regval = getreg32(STM32_RCC_AHB4ENR); -#ifdef CONFIG_STM32H5_OTFDEC1EN +#ifdef CONFIG_STM32_OTFDEC1 /* On-the-fly-decryption module clock enable */ regval |= RCC_AHB4ENR_OTFDEC1EN; @@ -413,7 +413,7 @@ static inline void rcc_enableapb1l(void) regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32H5_I3C1 +#ifdef CONFIG_STM32_I3C1 /* Bit 23: I3C1 clock enable */ regval |= RCC_APB1LENR_I3C1EN; @@ -607,7 +607,7 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#if defined(CONFIG_STM32H5_SBS) || defined(CONFIG_STM32_ETHMAC) +#if defined(CONFIG_STM32_SBS) || defined(CONFIG_STM32_ETHMAC) /* Bit 1: SBS clock enable */ regval |= RCC_APB3ENR_SBSEN; @@ -637,7 +637,7 @@ static inline void rcc_enableapb3(void) regval |= RCC_APB3ENR_I2C4EN; #endif -#ifdef CONFIG_STM32H5_I3C2 +#ifdef CONFIG_STM32_I3C2 /* Bit 9: I3C2 clock enable */ regval |= RCC_APB3ENR_I3C2EN; @@ -667,7 +667,7 @@ static inline void rcc_enableapb3(void) regval |= RCC_APB3ENR_LPTIM5EN; #endif -#ifdef CONFIG_STM32H5_LPTIM6 +#ifdef CONFIG_STM32_LPTIM6 /* Bit 15: LPTIM6 clock enable */ regval |= RCC_APB3ENR_LPTIM6EN;
