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commit 20f15ba2e3c9a2e654393234a96781d290ba19ec Author: raiden00pl <[email protected]> AuthorDate: Sun Aug 16 11:18:08 2026 +0200 arch/arm/stm32f7: use common Kconfig symbols CONFIG_STM32F7_LCD_BACKLIGHT is not defined by any Kconfig, so the LTDC backlight control is dead code. CONFIG_STM32F7_PLLSAI and CONFIG_STM32F7_PLLI2S are defined by the board.h files, and the common SPI test helper names its mode macros CONFIG_STM32F7_SPIx_TEST_MODE. Use the common CONFIG_STM32_* names everywhere. Also drop the misspelled CONFIG_STM32F7_STM33F75XX from the DMA chip check, which already tests CONFIG_STM32_STM32F75XX. The CAN section of the STM32F7 documentation names the options CONFIG_STM32F7F7_CANx, which has a duplicated family prefix and never existed. Use the common names there too. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- Documentation/platforms/arm/stm32f7/index.rst | 8 +-- arch/arm/include/stm32f7/chip.h | 6 +- .../src/stm32f7/hardware/stm32f72xx73xx_flash.h | 4 +- .../src/stm32f7/hardware/stm32f74xx75xx_flash.h | 4 +- .../src/stm32f7/hardware/stm32f76xx77xx_flash.h | 4 +- arch/arm/src/stm32f7/stm32_adc.c | 6 +- arch/arm/src/stm32f7/stm32_adc.h | 8 +-- arch/arm/src/stm32f7/stm32_allocateheap.c | 2 +- arch/arm/src/stm32f7/stm32_bbsram.h | 2 +- arch/arm/src/stm32f7/stm32_config.h | 72 +++++++++++----------- arch/arm/src/stm32f7/stm32_dma.c | 2 +- arch/arm/src/stm32f7/stm32_ethernet.c | 4 +- arch/arm/src/stm32f7/stm32_i2s.c | 6 +- arch/arm/src/stm32f7/stm32_irq.c | 8 +-- arch/arm/src/stm32f7/stm32_ltdc.c | 26 ++++---- arch/arm/src/stm32f7/stm32_ltdc.h | 4 +- arch/arm/src/stm32f7/stm32_otgdev.c | 2 +- arch/arm/src/stm32f7/stm32_otghost.c | 48 +++++++-------- arch/arm/src/stm32f7/stm32_pwm.c | 24 ++++---- arch/arm/src/stm32f7/stm32_pwm.h | 8 +-- arch/arm/src/stm32f7/stm32_qencoder.h | 20 +++--- arch/arm/src/stm32f7/stm32_sai.c | 48 +++++++-------- arch/arm/src/stm32f7/stm32_tim.c | 46 +++++++------- arch/arm/src/stm32f7/stm32_usbhost.h | 8 +-- arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c | 4 +- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 4 +- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 4 +- boards/arm/common/stm32/src/stm32_spitest.c | 36 +++++------ boards/arm/stm32f7/nucleo-f722ze/include/board.h | 4 +- boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c | 2 +- boards/arm/stm32f7/nucleo-f746zg/include/board.h | 4 +- boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c | 2 +- boards/arm/stm32f7/nucleo-f767zi/include/board.h | 4 +- boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c | 2 +- boards/arm/stm32f7/stm32f746-ws/include/board.h | 4 +- .../arm/stm32f7/stm32f746g-disco/include/board.h | 4 +- .../arm/stm32f7/stm32f746g-disco/src/stm32_boot.c | 2 +- .../stm32f7/stm32f777zit6-meadow/include/board.h | 4 +- 38 files changed, 225 insertions(+), 225 deletions(-) diff --git a/Documentation/platforms/arm/stm32f7/index.rst b/Documentation/platforms/arm/stm32f7/index.rst index 6f525e8e2fe..65f9298c577 100644 --- a/Documentation/platforms/arm/stm32f7/index.rst +++ b/Documentation/platforms/arm/stm32f7/index.rst @@ -184,8 +184,8 @@ Options: CAN --- -- CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32F7F7_CAN1 or - CONFIG_STM32F7F7_CAN2 must also be defined) +- CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or + CONFIG_STM32_CAN2 must also be defined) - CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default Standard 11-bit IDs. @@ -202,9 +202,9 @@ CAN - CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback mode for testing. The STM32F7 CAN driver does support loopback mode. -- CONFIG_STM32F7F7_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7F7_CAN1 is defined. +- CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. -- CONFIG_STM32F7F7_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7F7_CAN2 is defined. +- CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. - CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 9fe7f2cd2e0..2d17d6538fc 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -181,8 +181,8 @@ * Parts STM32F74xxG have 1024Kb of FLASH * Parts STM32F74xxI have 2048Kb of FLASH * - * The correct FLASH size will be set CONFIG_STM32F7_FLASH_CONFIG_x - * or overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * The correct FLASH size will be set CONFIG_STM32_FLASH_CONFIG_x + * or overridden with CONFIG_STM32_FLASH_OVERRIDE_x * */ #if defined(CONFIG_ARCH_CHIP_STM32F722RC) || \ @@ -423,7 +423,7 @@ #else #define STM32_NHASH 0 /* No HASH engine */ #endif -#if defined(CONFIG_STM32F7_HAVE_DFSDM) +#if defined(CONFIG_STM32_HAVE_DFSDM) #define STM32_NDFSDM 4 /* One set of 4 Digital filters */ #else #define STM32_NDFSDM 0 /* No Digital filters */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h index c18724aa2e0..e24ebcdafbc 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h @@ -30,9 +30,9 @@ /* Flash size is known from the chip selection: * * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. - * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * This value can be overridden with CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32F72xxC have 256Kb of FLASH * Parts STM32F72xxE have 512Kb of FLASH diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h index e5bb26ef1d5..3ed343c6612 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h @@ -30,9 +30,9 @@ /* Flash size is known from the chip selection: * * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. - * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * This value can be overridden with CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h index c98d3c72aa0..99463d16136 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h @@ -30,9 +30,9 @@ /* Flash size is known from the chip selection: * * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. - * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * This value can be overridden with CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index c47336e6df2..90f56057b4c 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -3032,7 +3032,7 @@ static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) * The logic allow initialize ADC regular and injected channels. * * The number of injected channels for given ADC is selected from Kconfig - * with CONFIG_STM32F7_ADCx_INJECTED_CHAN definitions + * with CONFIG_STM32_ADCx_INJECTED_CHAN definitions * * The number of regular channels is obtained from the equation: * @@ -3056,9 +3056,9 @@ static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) * chanlist[channels] -> ADC_JSQR_ISQy * * where: - * y = CONFIG_STM32F7_ADCx_INJECTED_CHAN, and y > 0 + * y = CONFIG_STM32_ADCx_INJECTED_CHAN, and y > 0 * - * If CONFIG_STM32F7_ADCx_INJECTED_CHAN = 0, then all channels from + * If CONFIG_STM32_ADCx_INJECTED_CHAN = 0, then all channels from * chanlist are regular channels. * * Input Parameters: diff --git a/arch/arm/src/stm32f7/stm32_adc.h b/arch/arm/src/stm32f7/stm32_adc.h index 8eb3e8a3d1d..867966ee491 100644 --- a/arch/arm/src/stm32f7/stm32_adc.h +++ b/arch/arm/src/stm32f7/stm32_adc.h @@ -58,8 +58,8 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32F7_TIMn is defined then - * CONFIG_STM32F7_TIMn_ADC must also be defined to indicate that timer "n" + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" * is intended to be used for that purpose. Timers 1-6 and 8 may be used. */ @@ -408,9 +408,9 @@ /* EXTSEL configuration *****************************************************/ /* NOTE: - * this configuration if used only if CONFIG_STM32F7_TIMx_ADCy is selected. + * this configuration if used only if CONFIG_STM32_TIMx_ADCy is selected. * You can still connect the ADC with a timer trigger using the - * CONFIG_STM32F7_ADCx_EXTSEL option. + * CONFIG_STM32_ADCx_EXTSEL option. */ #if defined(CONFIG_STM32_TIM1_ADC1) diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 024e37de43c..8c0a72c9ce1 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -63,7 +63,7 @@ * to be present in the NuttX configuration file: * * CONFIG_STM32_FMC=y : Enables the FMC - * CONFIG_STM32F7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC. + * CONFIG_STM32_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC. * Either of these autoselects * CONFIG_ARCH_HAVE_HEAP2 * which is what we are interested in here. diff --git a/arch/arm/src/stm32f7/stm32_bbsram.h b/arch/arm/src/stm32f7/stm32_bbsram.h index 7d6e8e3608e..a660e0e02b9 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.h +++ b/arch/arm/src/stm32f7/stm32_bbsram.h @@ -25,7 +25,7 @@ /**************************************************************************** * The purpose of this driver is to add battery backup file to the file - * system. There can be CONFIG_STM32F7_BBRSRAM_COUNT files defined. + * system. There can be CONFIG_STM32_BBRSRAM_COUNT files defined. * These files are of fixed size up to the maximum of the backing 4K SRAM. * * If CONFIG_SAVE_CRASHDUMP is defined The driver also supports a feature diff --git a/arch/arm/src/stm32f7/stm32_config.h b/arch/arm/src/stm32f7/stm32_config.h index f4894e9ec7f..c017552e64d 100644 --- a/arch/arm/src/stm32f7/stm32_config.h +++ b/arch/arm/src/stm32f7/stm32_config.h @@ -38,28 +38,28 @@ /* GPIO IRQs ****************************************************************/ -#ifndef CONFIG_STM32F7_GPIO_IRQ -# undef CONFIG_STM32F7_GPIOA_IRQ -# undef CONFIG_STM32F7_GPIOB_IRQ -# undef CONFIG_STM32F7_GPIOC_IRQ -# undef CONFIG_STM32F7_GPIOD_IRQ -# undef CONFIG_STM32F7_GPIOE_IRQ +#ifndef CONFIG_STM32_GPIO_IRQ +# undef CONFIG_STM32_GPIOA_IRQ +# undef CONFIG_STM32_GPIOB_IRQ +# undef CONFIG_STM32_GPIOC_IRQ +# undef CONFIG_STM32_GPIOD_IRQ +# undef CONFIG_STM32_GPIOE_IRQ #endif #if STM32_NPORTS < 1 -# undef CONFIG_STM32F7_GPIOA_IRQ +# undef CONFIG_STM32_GPIOA_IRQ #endif #if STM32_NPORTS < 2 -# undef CONFIG_STM32F7_GPIOB_IRQ +# undef CONFIG_STM32_GPIOB_IRQ #endif #if STM32_NPORTS < 3 -# undef CONFIG_STM32F7_GPIOC_IRQ +# undef CONFIG_STM32_GPIOC_IRQ #endif #if STM32_NPORTS < 4 -# undef CONFIG_STM32F7_GPIOD_IRQ +# undef CONFIG_STM32_GPIOD_IRQ #endif #if STM32_NPORTS < 5 -# undef CONFIG_STM32F7_GPIOE_IRQ +# undef CONFIG_STM32_GPIOE_IRQ #endif /* UARTs ********************************************************************/ @@ -67,22 +67,22 @@ /* Don't enable UARTs not supported by the chip. */ #if STM32_NUART < 1 -# undef CONFIG_STM32F7_UART0 -# undef CONFIG_STM32F7_UART1 -# undef CONFIG_STM32F7_UART2 -# undef CONFIG_STM32F7_UART3 +# undef CONFIG_STM32_UART0 +# undef CONFIG_STM32_UART1 +# undef CONFIG_STM32_UART2 +# undef CONFIG_STM32_UART3 # undef CONFIG_STM32_UART4 #elif STM32_NUART < 2 -# undef CONFIG_STM32F7_UART1 -# undef CONFIG_STM32F7_UART2 -# undef CONFIG_STM32F7_UART3 +# undef CONFIG_STM32_UART1 +# undef CONFIG_STM32_UART2 +# undef CONFIG_STM32_UART3 # undef CONFIG_STM32_UART4 #elif STM32_NUART < 3 -# undef CONFIG_STM32F7_UART2 -# undef CONFIG_STM32F7_UART3 +# undef CONFIG_STM32_UART2 +# undef CONFIG_STM32_UART3 # undef CONFIG_STM32_UART4 #elif STM32_NUART < 4 -# undef CONFIG_STM32F7_UART3 +# undef CONFIG_STM32_UART3 # undef CONFIG_STM32_UART4 #elif STM32_NUART < 5 # undef CONFIG_STM32_UART4 @@ -91,8 +91,8 @@ /* Are any UARTs enabled? */ #undef HAVE_UART_DEVICE -#if defined(CONFIG_STM32F7_UART0) || defined(CONFIG_STM32F7_UART1) || \ - defined(CONFIG_STM32F7_UART2) || defined(CONFIG_STM32F7_UART3) || \ +#if defined(CONFIG_STM32_UART0) || defined(CONFIG_STM32_UART1) || \ + defined(CONFIG_STM32_UART2) || defined(CONFIG_STM32_UART3) || \ defined(CONFIG_STM32_UART4) # define HAVE_UART_DEVICE 1 #endif @@ -104,7 +104,7 @@ */ #ifndef CONFIG_USART0_SERIALDRIVER -# undef CONFIG_STM32F7_USART0 +# undef CONFIG_STM32_USART0 #endif #ifndef CONFIG_USART1_SERIALDRIVER # undef CONFIG_STM32_USART1 @@ -116,7 +116,7 @@ /* Don't enable USARTs not supported by the chip. */ #if STM32_NUSART < 1 -# undef CONFIG_STM32F7_USART0 +# undef CONFIG_STM32_USART0 # undef CONFIG_STM32_USART1 # undef CONFIG_STM32_USART2 #elif STM32_NUSART < 2 @@ -128,7 +128,7 @@ /* Are any USARTs enabled? */ -#if defined(CONFIG_STM32F7_USART0) || defined(CONFIG_STM32_USART1) || \ +#if defined(CONFIG_STM32_USART0) || defined(CONFIG_STM32_USART1) || \ defined(CONFIG_STM32_USART2) # undef HAVE_UART_DEVICE # define HAVE_UART_DEVICE 1 @@ -163,7 +163,7 @@ */ #undef HAVE_SERIAL_CONSOLE -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART0) +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART0) # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE @@ -172,7 +172,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART1) +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART1) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE @@ -181,7 +181,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART2) +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART2) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE @@ -190,7 +190,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART3) +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART3) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -208,7 +208,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART0) +#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART0) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -251,21 +251,21 @@ /* Don't enable SPI peripherals not supported by the chip. */ #if CHIP_NSPI < 1 -# undef CONFIG_STM32F7_SPI0 +# undef CONFIG_STM32_SPI0 # undef CONFIG_STM32_SPI1 #elif CHIP_NSPI < 2 # undef CONFIG_STM32_SPI1 #endif -#ifndef CONFIG_STM32F7_HAVE_SPI -# undef CONFIG_STM32F7_SPI0 +#ifndef CONFIG_STM32_HAVE_SPI +# undef CONFIG_STM32_SPI0 # undef CONFIG_STM32_SPI1 #endif /* Are any SPI peripherals enabled? */ -#if !defined(CONFIG_STM32F7_SPI0) && !defined(CONFIG_STM32F7_SPI0) -# undef CONFIG_STM32F7_HAVE_SPI +#if !defined(CONFIG_STM32_SPI0) && !defined(CONFIG_STM32_SPI0) +# undef CONFIG_STM32_HAVE_SPI #endif /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index c56d8bdf7c5..a5685d641d3 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -46,7 +46,7 @@ * families */ -#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32F7_STM33F75XX) \ +#if defined(CONFIG_STM32_STM32F72XX) \ || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 8b281e2f31b..666186b2ceb 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -189,8 +189,8 @@ #define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 15) & ~15) -#ifdef CONFIG_STM32F7_ETH_BUFSIZE -# define ETH_BUFSIZE CONFIG_STM32F7_ETH_BUFSIZE +#ifdef CONFIG_STM32_ETH_BUFSIZE +# define ETH_BUFSIZE CONFIG_STM32_ETH_BUFSIZE #else # define ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE #endif diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c index 13449214c36..e00f9d7b03c 100644 --- a/arch/arm/src/stm32f7/stm32_i2s.c +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -211,8 +211,8 @@ #ifndef CONFIG_DEBUG_I2S_INFO # undef CONFIG_STM32_I2S_DMADEBUG # undef CONFIG_STM32_I2S_REGDEBUG -# undef CONFIG_STM32F7_I2S_QDEBUG -# undef CONFIG_STM32F7_I2S_DUMPBUFFERS +# undef CONFIG_STM32_I2S_QDEBUG +# undef CONFIG_STM32_I2S_DUMPBUFFERS #endif /* The I2S can handle most any bit width from 8 to 32. However, the DMA @@ -379,7 +379,7 @@ static void i2s_dump_regs(struct stm32_i2s_s *priv, const char *msg); # define i2s_dump_regs(s,m) #endif -#ifdef CONFIG_STM32F7_I2S_DUMPBUFFERS +#ifdef CONFIG_STM32_I2S_DUMPBUFFERS # define i2s_init_buffer(b,s) memset(b, 0x55, s); # define i2s_dump_buffer(m,b,s) lib_dumpbuffer(m,b,s) #else diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c index 0d7080377e8..5b768bb9bcd 100644 --- a/arch/arm/src/stm32f7/stm32_irq.c +++ b/arch/arm/src/stm32f7/stm32_irq.c @@ -40,7 +40,7 @@ #include "ram_vectors.h" #include "arm_internal.h" -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ # include "stm32_gpio.h" #endif @@ -402,7 +402,7 @@ void up_irqinitialize(void) * GPIO pins. */ -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ stm32_gpioirqinitialize(); #endif @@ -446,7 +446,7 @@ void up_disable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ @@ -493,7 +493,7 @@ void up_enable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c index 2901e7ad46d..8c8acb4fec6 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.c +++ b/arch/arm/src/stm32f7/stm32_ltdc.c @@ -213,36 +213,36 @@ #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT) #ifdef CONFIG_STM32_LTDC_L2 -# ifndef CONFIG_STM32F7_LTDC_L2_WIDTH -# define CONFIG_STM32F7_LTDC_L2_WIDTH STM32_LTDC_WIDTH +# ifndef CONFIG_STM32_LTDC_L2_WIDTH +# define CONFIG_STM32_LTDC_L2_WIDTH STM32_LTDC_WIDTH # endif -# if CONFIG_STM32F7_LTDC_L2_WIDTH > STM32_LTDC_WIDTH +# if CONFIG_STM32_LTDC_L2_WIDTH > STM32_LTDC_WIDTH # error Width of Layer 2 exceeds the width of the display # endif -# ifndef CONFIG_STM32F7_LTDC_L2_HEIGHT -# define CONFIG_STM32F7_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT +# ifndef CONFIG_STM32_LTDC_L2_HEIGHT +# define CONFIG_STM32_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT # endif -# if CONFIG_STM32F7_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT +# if CONFIG_STM32_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT # error Height of Layer 2 exceeds the height of the display # endif # if STM32_LTDC_L2_BPP == 8 -# define STM32_LTDC_L2_STRIDE (CONFIG_STM32F7_LTDC_L2_WIDTH) +# define STM32_LTDC_L2_STRIDE (CONFIG_STM32_LTDC_L2_WIDTH) # elif STM32_LTDC_L2_BPP == 16 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32F7_LTDC_L2_WIDTH * 16 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 16 + 7) / 8) # elif STM32_LTDC_L2_BPP == 24 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32F7_LTDC_L2_WIDTH * 24 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 24 + 7) / 8) # elif STM32_LTDC_L2_BPP == 32 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32F7_LTDC_L2_WIDTH * 32 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 32 + 7) / 8) # else # error Undefined or unrecognized base resolution # endif # define STM32_LTDC_L2_FBSIZE (STM32_LTDC_L2_STRIDE * \ - CONFIG_STM32F7_LTDC_L2_HEIGHT) + CONFIG_STM32_LTDC_L2_HEIGHT) #else # define STM32_LTDC_L2_FBSIZE (0) @@ -3046,7 +3046,7 @@ int stm32_ltdcinitialize(void) #endif /* Enable the backlight */ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LTDC_BACKLIGHT stm32_backlight(true); #endif @@ -3132,7 +3132,7 @@ void stm32_ltdcuninitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LTDC_BACKLIGHT void stm32_backlight(bool blon) { /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ diff --git a/arch/arm/src/stm32f7/stm32_ltdc.h b/arch/arm/src/stm32f7/stm32_ltdc.h index d7a432a01cd..8de1ba36591 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.h +++ b/arch/arm/src/stm32f7/stm32_ltdc.h @@ -91,12 +91,12 @@ struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); * Name: stm32_lcd_backlight * * Description: - * If CONFIG_STM32F7_LCD_BACKLIGHT is defined, then the board-specific + * If CONFIG_STM32_LTDC_BACKLIGHT is defined, then the board-specific * logic must provide this interface to turn the backlight on and off. * ****************************************************************************/ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LTDC_BACKLIGHT void stm32_backlight(bool blon); #endif #endif /* __ARCH_ARM_SRC_STM32F7_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index 803438a0dd4..96be757e9e3 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -5991,4 +5991,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32F7_OTGDEV */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGDEV */ diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index 8d7565adf60..d66c084a888 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -78,14 +78,14 @@ * * Options: * - * CONFIG_STM32F7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32F7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 - * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 + * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. @@ -101,26 +101,26 @@ /* Default RxFIFO size */ -#ifndef CONFIG_STM32F7_OTG_RXFIFO_SIZE -# define CONFIG_STM32F7_OTG_RXFIFO_SIZE 128 +#ifndef CONFIG_STM32_OTG_RXFIFO_SIZE +# define CONFIG_STM32_OTG_RXFIFO_SIZE 128 #endif /* Default host non-periodic Tx FIFO size */ -#ifndef CONFIG_STM32F7_OTG_NPTXFIFO_SIZE -# define CONFIG_STM32F7_OTG_NPTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTG_NPTXFIFO_SIZE +# define CONFIG_STM32_OTG_NPTXFIFO_SIZE 96 #endif /* Default host periodic Tx fifo size register */ -#ifndef CONFIG_STM32F7_OTG_PTXFIFO_SIZE -# define CONFIG_STM32F7_OTG_PTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTG_PTXFIFO_SIZE +# define CONFIG_STM32_OTG_PTXFIFO_SIZE 96 #endif /* Maximum size of a descriptor */ -#ifndef CONFIG_STM32F7_OTG_DESCSIZE -# define CONFIG_STM32F7_OTG_DESCSIZE 128 +#ifndef CONFIG_STM32_OTG_DESCSIZE +# define CONFIG_STM32_OTG_DESCSIZE 128 #endif /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ @@ -380,7 +380,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); /* Second level interrupt handlers */ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); #endif static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); @@ -2987,7 +2987,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) { /* Handle SOF interrupt */ @@ -3555,7 +3555,7 @@ static int stm32_gint_isr(int irq, void *context, void *arg) /* Handle the start of frame interrupt */ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR if ((pending & OTG_GINT_SOF) != 0) { usbhost_vtrace1(OTG_VTRACE1_GINT_SOF, 0); @@ -3721,7 +3721,7 @@ static inline void stm32_hostinit_enable(void) * OTG_GINT_DISC : Disconnect detected interrupt */ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR regval |= (OTG_GINT_SOF | OTG_GINT_RXFLVL | OTG_GINT_IISOOXFR | OTG_GINT_HPRT | OTG_GINT_HC | OTG_GINT_DISC); #else @@ -4245,7 +4245,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* There is no special memory requirement for the STM32. */ - alloc = kmm_malloc(CONFIG_STM32F7_OTG_DESCSIZE); + alloc = kmm_malloc(CONFIG_STM32_OTG_DESCSIZE); if (!alloc) { return -ENOMEM; @@ -4254,7 +4254,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* Return the allocated address and size of the descriptor buffer */ *buffer = alloc; - *maxlen = CONFIG_STM32F7_OTG_DESCSIZE; + *maxlen = CONFIG_STM32_OTG_DESCSIZE; return OK; } @@ -5121,21 +5121,21 @@ static void stm32_host_initialize(struct stm32_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32F7_OTG_RXFIFO_SIZE); - offset = CONFIG_STM32F7_OTG_RXFIFO_SIZE; + stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32_OTG_RXFIFO_SIZE); + offset = CONFIG_STM32_OTG_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ regval = (offset | - (CONFIG_STM32F7_OTG_NPTXFIFO_SIZE << + (CONFIG_STM32_OTG_NPTXFIFO_SIZE << OTG_HNPTXFSIZ_NPTXFD_SHIFT)); stm32_putreg(STM32_OTG_HNPTXFSIZ, regval); - offset += CONFIG_STM32F7_OTG_NPTXFIFO_SIZE; + offset += CONFIG_STM32_OTG_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ regval = (offset | - (CONFIG_STM32F7_OTG_PTXFIFO_SIZE << + (CONFIG_STM32_OTG_PTXFIFO_SIZE << OTG_HPTXFSIZ_PTXFD_SHIFT)); stm32_putreg(STM32_OTG_HPTXFSIZ, regval); diff --git a/arch/arm/src/stm32f7/stm32_pwm.c b/arch/arm/src/stm32f7/stm32_pwm.c index b766be473f1..1d7edacc121 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.c +++ b/arch/arm/src/stm32f7/stm32_pwm.c @@ -163,8 +163,8 @@ /* Break support */ -#if defined(CONFIG_STM32F7_TIM1_BREAK1) || defined(CONFIG_STM32F7_TIM1_BREAK2) || \ - defined(CONFIG_STM32F7_TIM8_BREAK1) || defined(CONFIG_STM32F7_TIM8_BREAK2) +#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ + defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) # defined HAVE_BREAK #endif @@ -385,14 +385,14 @@ static struct stm32_pwmchan_s g_pwm1channels[] = #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32F7_TIM1_BREAK1 +#ifdef CONFIG_STM32_TIM1_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32F7_TIM1_BRK1POL, + .pol1 = CONFIG_STM32_TIM1_BRK1POL, #endif -#ifdef CONFIG_STM32F7_TIM1_BREAK2 +#ifdef CONFIG_STM32_TIM1_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32F7_TIM1_BRK2POL, - .flt2 = CONFIG_STM32F7_TIM1_BRK2FLT, + .pol2 = CONFIG_STM32_TIM1_BRK2POL, + .flt2 = CONFIG_STM32_TIM1_BRK2FLT, #endif }, #endif @@ -930,14 +930,14 @@ static struct stm32_pwmchan_s g_pwm8channels[] = #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32F7_TIM8_BREAK1 +#ifdef CONFIG_STM32_TIM8_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32F7_TIM8_BRK1POL, + .pol1 = CONFIG_STM32_TIM8_BRK1POL, #endif -#ifdef CONFIG_STM32F7_TIM8_BREAK2 +#ifdef CONFIG_STM32_TIM8_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32F7_TIM8_BRK2POL, - .flt2 = CONFIG_STM32F7_TIM8_BRK2FLT, + .pol2 = CONFIG_STM32_TIM8_BRK2POL, + .flt2 = CONFIG_STM32_TIM8_BRK2FLT, #endif }, #endif diff --git a/arch/arm/src/stm32f7/stm32_pwm.h b/arch/arm/src/stm32f7/stm32_pwm.h index 637833554ea..0aa3aed6d71 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.h +++ b/arch/arm/src/stm32f7/stm32_pwm.h @@ -52,7 +52,7 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. - * If CONFIG_STM32F7_TIMn is defined then the CONFIG_STM32F7_TIMn_PWM must + * If CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must * also be defined to indicate that timer "n" is intended to be used for * pulsed output signal generation. */ @@ -98,8 +98,8 @@ * pulses */ -#undef CONFIG_STM32F7_TIM6_PWM -#undef CONFIG_STM32F7_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ @@ -326,7 +326,7 @@ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. In the * case where there are multiple pin selections, the correct setting must be * provided in the arch/board/board.h file. diff --git a/arch/arm/src/stm32f7/stm32_qencoder.h b/arch/arm/src/stm32f7/stm32_qencoder.h index 40b2f6f92e1..cb0399814da 100644 --- a/arch/arm/src/stm32f7/stm32_qencoder.h +++ b/arch/arm/src/stm32f7/stm32_qencoder.h @@ -38,8 +38,8 @@ ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32F7_TIMn is defined - * then the CONFIG_STM32F7_TIMn_QE must also be defined to indicate that + * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined + * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that * timer "n" is intended to be used for as a quadrature encoder. */ @@ -66,14 +66,14 @@ * (at least for the STM32 F7) */ -#undef CONFIG_STM32F7_TIM6_QE -#undef CONFIG_STM32F7_TIM7_QE -#undef CONFIG_STM32F7_TIM9_QE -#undef CONFIG_STM32F7_TIM10_QE -#undef CONFIG_STM32F7_TIM11_QE -#undef CONFIG_STM32F7_TIM12_QE -#undef CONFIG_STM32F7_TIM13_QE -#undef CONFIG_STM32F7_TIM14_QE +#undef CONFIG_STM32_TIM6_QE +#undef CONFIG_STM32_TIM7_QE +#undef CONFIG_STM32_TIM9_QE +#undef CONFIG_STM32_TIM10_QE +#undef CONFIG_STM32_TIM11_QE +#undef CONFIG_STM32_TIM12_QE +#undef CONFIG_STM32_TIM13_QE +#undef CONFIG_STM32_TIM14_QE /**************************************************************************** * Included Files diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index 25aaf8d0063..ea96a7e2a0c 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -94,16 +94,16 @@ # error "Interrupt driven SAI not yet supported" #endif -#ifndef CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE -# define CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE (48000) +#ifndef CONFIG_STM32_SAI_DEFAULT_SAMPLERATE +# define CONFIG_STM32_SAI_DEFAULT_SAMPLERATE (48000) #endif -#ifndef CONFIG_STM32F7_SAI_DEFAULT_DATALEN -# define CONFIG_STM32F7_SAI_DEFAULT_DATALEN (16) +#ifndef CONFIG_STM32_SAI_DEFAULT_DATALEN +# define CONFIG_STM32_SAI_DEFAULT_DATALEN (16) #endif -#ifndef CONFIG_STM32F7_SAI_MAXINFLIGHT -# define CONFIG_STM32F7_SAI_MAXINFLIGHT (16) +#ifndef CONFIG_STM32_SAI_MAXINFLIGHT +# define CONFIG_STM32_SAI_MAXINFLIGHT (16) #endif #ifdef CONFIG_STM32_SAI1 @@ -121,14 +121,14 @@ #ifdef CONFIG_STM32_SAI_DMA /* SAI DMA priority */ -# if defined(CONFIG_STM32F7_SAI_DMAPRIO) -# define SAI_DMA_PRIO CONFIG_STM32F7_SAI_DMAPRIO +# if defined(CONFIG_STM32_SAI_DMAPRIO) +# define SAI_DMA_PRIO CONFIG_STM32_SAI_DMAPRIO # else # define SAI_DMA_PRIO DMA_SCR_PRIVERYHI # endif # if (SAI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32F7_SAI_DMAPRIO" +# error "Illegal value for CONFIG_STM32_SAI_DMAPRIO" # endif /* DMA channel/stream configuration register settings. The following @@ -213,7 +213,7 @@ struct stm32f7_sai_s sem_t bufsem; /* Buffer wait semaphore */ struct sai_buffer_s *freelist; /* A list a free buffer containers */ - struct sai_buffer_s containers[CONFIG_STM32F7_SAI_MAXINFLIGHT]; + struct sai_buffer_s containers[CONFIG_STM32_SAI_MAXINFLIGHT]; }; /**************************************************************************** @@ -289,9 +289,9 @@ static struct stm32f7_sai_s g_sai1a_priv = #ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_A, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif @@ -310,9 +310,9 @@ static struct stm32f7_sai_s g_sai1b_priv = #ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_B, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif @@ -333,9 +333,9 @@ static struct stm32f7_sai_s g_sai2a_priv = #ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_A, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif @@ -354,9 +354,9 @@ static struct stm32f7_sai_s g_sai2b_priv = #ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_B, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif @@ -1485,7 +1485,7 @@ static void sai_buf_initialize(struct stm32f7_sai_s *priv) int i; priv->freelist = NULL; - for (i = 0; i < CONFIG_STM32F7_SAI_MAXINFLIGHT; i++) + for (i = 0; i < CONFIG_STM32_SAI_MAXINFLIGHT; i++) { sai_buf_free(priv, &priv->containers[i]); } @@ -1520,7 +1520,7 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv) /* Configure the data width */ sai_datawidth((struct i2s_dev_s *)priv, - CONFIG_STM32F7_SAI_DEFAULT_DATALEN); + CONFIG_STM32_SAI_DEFAULT_DATALEN); #ifdef CONFIG_STM32_SAI_DMA /* Get DMA channel */ diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c index 6919283f948..513396bd96f 100644 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ b/arch/arm/src/stm32f7/stm32_tim.c @@ -53,20 +53,20 @@ * Such special purposes include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32F7_TIMn is defined then the CONFIG_STM32F7_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32F7_TIMn is - * defined then CONFIG_STM32F7_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32F7_TIMn is defined - * then CONFIG_STM32F7_TIMn_DAC may also be defined to indicate that timer + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer * "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32F7_TIMn is defined then - * CONFIG_STM32F7_TIMn_QE may also be defined to indicate that timer + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer * "n" is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. @@ -92,40 +92,40 @@ defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) # undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32F7_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32F7_TIM6_QE) +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) # undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32F7_TIM7_PWM) || defined (CONFIG_STM32F7_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32F7_TIM7_QE) +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) # undef CONFIG_STM32_TIM7 #endif #if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) # undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32F7_TIM9_ADC) || \ - defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32F7_TIM9_QE) +#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32_TIM9_ADC) || \ + defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32_TIM9_QE) # undef CONFIG_STM32_TIM9 #endif -#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32F7_TIM10_ADC) || \ - defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32F7_TIM10_QE) +#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32_TIM10_ADC) || \ + defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32_TIM10_QE) # undef CONFIG_STM32_TIM10 #endif -#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32F7_TIM11_ADC) || \ - defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32F7_TIM11_QE) +#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32_TIM11_ADC) || \ + defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32_TIM11_QE) # undef CONFIG_STM32_TIM11 #endif -#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32F7_TIM12_ADC) || \ - defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32F7_TIM12_QE) +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) # undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32F7_TIM13_ADC) || \ - defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32F7_TIM13_QE) +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) # undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32F7_TIM14_ADC) || \ - defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32F7_TIM14_QE) +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) # undef CONFIG_STM32_TIM14 #endif diff --git a/arch/arm/src/stm32f7/stm32_usbhost.h b/arch/arm/src/stm32f7/stm32_usbhost.h index 68eaee020a8..6a1500043ae 100644 --- a/arch/arm/src/stm32f7/stm32_usbhost.h +++ b/arch/arm/src/stm32f7/stm32_usbhost.h @@ -35,13 +35,13 @@ * * Options: * - * CONFIG_STM32F7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32F7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 629881f1196..5911b6a7139 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -857,7 +857,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32_PLLSAI) /* Configure PLLSAI */ @@ -912,7 +912,7 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32F7_PLLI2S) || \ +#if defined(CONFIG_STM32_PLLI2S) || \ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) /* Configure PLLI2S */ diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index fa7e56b6c6c..4da3ddffceb 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -852,7 +852,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32_PLLSAI) /* Configure PLLSAI */ @@ -897,7 +897,7 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32F7_PLLI2S) || \ +#if defined(CONFIG_STM32_PLLI2S) || \ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) /* Configure PLLI2S */ diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index e14d7017494..95eb7e6a592 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -872,7 +872,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32_PLLSAI) /* Configure PLLSAI */ @@ -921,7 +921,7 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32F7_PLLI2S) || \ +#if defined(CONFIG_STM32_PLLI2S) || \ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) diff --git a/boards/arm/common/stm32/src/stm32_spitest.c b/boards/arm/common/stm32/src/stm32_spitest.c index d1e048bb7ca..f5c628d00a5 100644 --- a/boards/arm/common/stm32/src/stm32_spitest.c +++ b/boards/arm/common/stm32/src/stm32_spitest.c @@ -45,43 +45,43 @@ #if defined(CONFIG_STM32_SPI1_TEST) # if defined(CONFIG_STM32_SPI1_TEST_MODE0) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE0 +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE0 # elif defined(CONFIG_STM32_SPI1_TEST_MODE1) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE1 +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE1 # elif defined(CONFIG_STM32_SPI1_TEST_MODE2) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE2 +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE2 # elif defined(CONFIG_STM32_SPI1_TEST_MODE3) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE3 +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE3 # else -# error "No CONFIG_STM32F7_SPI1_TEST_MODEx defined" +# error "No CONFIG_STM32_SPI1_TEST_MODEx defined" # endif #endif #if defined(CONFIG_STM32_SPI2_TEST) # if defined(CONFIG_STM32_SPI2_TEST_MODE0) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE0 +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE0 # elif defined(CONFIG_STM32_SPI2_TEST_MODE1) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE1 +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE1 # elif defined(CONFIG_STM32_SPI2_TEST_MODE2) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE2 +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE2 # elif defined(CONFIG_STM32_SPI2_TEST_MODE3) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE3 +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE3 # else -# error "No CONFIG_STM32F7_SPI2_TEST_MODEx defined" +# error "No CONFIG_STM32_SPI2_TEST_MODEx defined" # endif #endif #if defined(CONFIG_STM32_SPI3_TEST) # if defined(CONFIG_STM32_SPI3_TEST_MODE0) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE0 +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE0 # elif defined(CONFIG_STM32_SPI3_TEST_MODE1) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE1 +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE1 # elif defined(CONFIG_STM32_SPI3_TEST_MODE2) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE2 +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE2 # elif defined(CONFIG_STM32_SPI3_TEST_MODE3) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE3 +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE3 # else -# error "No CONFIG_STM32F7_SPI3_TEST_MODEx defined" +# error "No CONFIG_STM32_SPI3_TEST_MODEx defined" # endif #endif @@ -131,7 +131,7 @@ int stm32_spidev_bus_test(void) SPI_SETFREQUENCY(g_spi1, CONFIG_STM32_SPI1_TEST_FREQ); SPI_SETBITS(g_spi1, CONFIG_STM32_SPI1_TEST_BITS); - SPI_SETMODE(g_spi1, CONFIG_STM32F7_SPI1_TEST_MODE); + SPI_SETMODE(g_spi1, CONFIG_STM32_SPI1_TEST_MODE); SPI_EXCHANGE(g_spi1, tx, NULL, nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif @@ -149,7 +149,7 @@ int stm32_spidev_bus_test(void) SPI_SETFREQUENCY(g_spi2, CONFIG_STM32_SPI2_TEST_FREQ); SPI_SETBITS(g_spi2, CONFIG_STM32_SPI2_TEST_BITS); - SPI_SETMODE(g_spi2, CONFIG_STM32F7_SPI2_TEST_MODE); + SPI_SETMODE(g_spi2, CONFIG_STM32_SPI2_TEST_MODE); SPI_EXCHANGE(g_spi2, tx, NULL, nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif @@ -167,7 +167,7 @@ int stm32_spidev_bus_test(void) SPI_SETFREQUENCY(g_spi3, CONFIG_STM32_SPI3_TEST_FREQ); SPI_SETBITS(g_spi3, CONFIG_STM32_SPI3_TEST_BITS); - SPI_SETMODE(g_spi3, CONFIG_STM32F7_SPI3_TEST_MODE); + SPI_SETMODE(g_spi3, CONFIG_STM32_SPI3_TEST_MODE); SPI_EXCHANGE(g_spi3, tx, NULL, nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/include/board.h b/boards/arm/stm32f7/nucleo-f722ze/include/board.h index c7fb0260a56..7edaa52b8a8 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/include/board.h +++ b/boards/arm/stm32f7/nucleo-f722ze/include/board.h @@ -106,7 +106,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) @@ -125,7 +125,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c index 16862f9ada7..41464d917d5 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/include/board.h b/boards/arm/stm32f7/nucleo-f746zg/include/board.h index 1503c4fdd58..342f3803a47 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/include/board.h +++ b/boards/arm/stm32f7/nucleo-f746zg/include/board.h @@ -106,7 +106,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) @@ -125,7 +125,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c index da3915eacc6..b30ff20886d 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/include/board.h b/boards/arm/stm32f7/nucleo-f767zi/include/board.h index 2fc2127b7b3..7c0fce6faa1 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/include/board.h +++ b/boards/arm/stm32f7/nucleo-f767zi/include/board.h @@ -106,7 +106,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) @@ -125,7 +125,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c index b1bdae2f12b..c6224cb823c 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/stm32f746-ws/include/board.h b/boards/arm/stm32f7/stm32f746-ws/include/board.h index 6f605c17125..ed751486460 100644 --- a/boards/arm/stm32f7/stm32f746-ws/include/board.h +++ b/boards/arm/stm32f7/stm32f746-ws/include/board.h @@ -108,7 +108,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -127,7 +127,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h index c6c51607584..a0e9e92a51a 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h @@ -143,7 +143,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(BOARD_LTDC_PLLSAIN) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -168,7 +168,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(344) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(7) diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c index 32938e7d4c3..bc89ac56e8c 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c @@ -81,7 +81,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h index ba0702a92e8..e0c16934e09 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h @@ -148,7 +148,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(384) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -174,7 +174,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(4) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(4)
