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commit fcad1ef21dc136b3ece13771b1ad24c8c620bc5a Author: Jacob Dahl <[email protected]> AuthorDate: Sun Aug 30 14:17:52 2026 -0600 arch/arm/stm32f4: add STM32F412VG chip selection 100-pin 1MB F412 (LQFP/UFBGA). Without this, boards using STM32F412VGH6 have to select the 48-pin 512KB CE. STM32_NGPIO is 113 rather than the real 81 I/Os because STM32_NGPIO_PORTS is (N+15)>>4 and 81 yields six ports A-F, so PH0/PH1 could not be configured. 113 matches ZG and gives A-H. CE/ZG chip.h counts and the family HAVE_* list are corrected in the same change: CE has no FSMC, the die has TIM6/7/9-14 and SPI4/5, ZG USART is 4, I2S is 5. FSMC is only bonded on 100/144-pin, so HAVE_FSMC is selected on VG/ZG and not on CE. Signed-off-by: Jacob Dahl <[email protected]> --- arch/arm/include/stm32f4/chip.h | 38 ++++++++++++++++++++++++++++++++------ arch/arm/src/stm32f4/Kconfig | 13 +++++++++++++ 2 files changed, 45 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/stm32f4/chip.h b/arch/arm/include/stm32f4/chip.h index 9bf947fa6fc..e0ae3aac22a 100644 --- a/arch/arm/include/stm32f4/chip.h +++ b/arch/arm/include/stm32f4/chip.h @@ -225,15 +225,41 @@ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ #elif defined(CONFIG_ARCH_CHIP_STM32F412CE) /* UFQFPN48 package, 512Kb FLASH, 256KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC on the 48-pin package */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 5 /* I2S1-5 */ +# define STM32_NUSART 4 /* USART1, 2, 3 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* 2 CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 113 /* GPIOA-H. (N+15)>>4 is the port count; 34 yields A-C and drops H. */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F412VG) /* 100 pin LQFP/UFBGA package, 1MB FLASH, 256KiB SRAM */ # define STM32_NFSMC 1 /* FSMC */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ # define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 4 /* 16-bit general timers 9, 12, 13, and 14 without DMA */ -# define STM32_NBTIM 0 /* 2 basic timers TIM6 and TIM7 */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */ # define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ # define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 3 /* I2S1-3 */ +# define STM32_NI2S 5 /* I2S1-5 */ # define STM32_NUSART 4 /* USART1, 2, 3 and 6 */ # define STM32_NLPUART 0 /* No LPUART */ # define STM32_NI2C 3 /* I2C1-3 */ @@ -241,7 +267,7 @@ # define STM32_NSDIO 1 /* One SDIO interface */ # define STM32_NLCD 0 /* No LCD */ # define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 34 /* GPIOA-B (sans PB11) and 3 Bits of C */ +# define STM32_NGPIO 113 /* GPIOA-H. (N+15)>>4 is the port count; 81 yields A-F and drops H. */ # define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ # define STM32_NDAC 0 /* No DAC */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ @@ -259,8 +285,8 @@ # define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */ # define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ # define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 3 /* I2S1-3 */ -# define STM32_NUSART 6 /* USART1, 2, 3 and 6 */ +# define STM32_NI2S 5 /* I2S1-5 */ +# define STM32_NUSART 4 /* USART1, 2, 3 and 6 */ # define STM32_NLPUART 0 /* No LPUART */ # define STM32_NI2C 3 /* I2C1-3 */ # define STM32_NCAN 2 /* 2 CAN */ diff --git a/arch/arm/src/stm32f4/Kconfig b/arch/arm/src/stm32f4/Kconfig index 6d98f0577ac..bde2f644948 100644 --- a/arch/arm/src/stm32f4/Kconfig +++ b/arch/arm/src/stm32f4/Kconfig @@ -83,10 +83,17 @@ config ARCH_CHIP_STM32F412CE select STM32_STM32F4XXX select STM32_STM32F412 +config ARCH_CHIP_STM32F412VG + bool "STM32F412VG" + select STM32_STM32F4XXX + select STM32_STM32F412 + select STM32_HAVE_FSMC + config ARCH_CHIP_STM32F412ZG bool "STM32F412ZG" select STM32_STM32F4XXX select STM32_STM32F412 + select STM32_HAVE_FSMC config ARCH_CHIP_STM32F405RG bool "STM32F405RG" @@ -359,8 +366,12 @@ config STM32_STM32F412 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 select STM32_HAVE_TIM12 select STM32_HAVE_TIM13 select STM32_HAVE_TIM14 @@ -373,6 +384,8 @@ config STM32_STM32F412 select STM32_HAVE_SPI1 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 select STM32_HAVE_CAN1 select STM32_HAVE_CAN2 select STM32_HAVE_OTGFS
