daniel-p-carvalho opened a new pull request, #20180: URL: https://github.com/apache/nuttx/pull/20180
## Summary This PR implements lower-half PTP hardware clock operations (`struct ptp_lowerhalf_s` and `struct ptp_ops_s`) in the STM32 Ethernet driver (`arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c`) and registers it with the generic PTP clock framework (`drivers/timers/ptp_clock.c`) to expose the standard POSIX character driver `/dev/ptp0`. Supported operations: - `adjfine`: adjust PTP clock frequency in parts per billion (ppb) via the addend register (`PTPTSAR`) - `adjphase`: adjust PTP clock phase via hardware `TSSTU` - `adjtime`: shift PTP clock time by signed delta in nanoseconds - `gettime`: atomic double-read of hardware timestamp counter with second rollover handling - `settime`: initialize/jump hardware timestamp counter via `TSSTI` - `getres`: report 1 ns clock resolution It also includes necessary fixes to support hardware PTP clock operation: - Deliver direct raw hardware counter timestamps in `d_rxtimestamp` so the PTP servo can close the feedback loop against the master clock. - Fix RX timestamp conversion order so `stm32_eth_ptp_convert_rxtime()` runs before `pkt_input()`. - Fix sign bug in `stm32_eth_ptp_adjust()` where `uint64_t addend` promoted negative ppb adjustments to unsigned, corrupting frequency trim for crystals running fast. - Add `TMRDEPPATH`/`TMRVPATH` for PTP clock drivers in `drivers/timers/Make.defs`. - Set `ETH_MACCR_ROD` to disable reception of self-transmitted frames. Follow-up to #20148 per @xiaoxiang781216's review suggestion to replace custom socket ioctls (`SIOCS_PTP_ADJFREQ`, `SIOCS_PTP_ADJPHASE`) with the standard POSIX character driver `/dev/ptp0`. Hardware transmit timestamping will follow in a separate PR aligned with #20161 (`SO_TIMESTAMPING`). ## Impact Enables standard POSIX hardware clock disciplining via `clock_adjtime()` on `/dev/ptp0` on STM32 Ethernet interfaces. Fully compatible with `ptpd -p /dev/ptp0`. ## Testing Tested on real hardware (`stm32f4discovery-ext:ethraw` / STM32F407) connected via L2 Ethernet P2P to a GNSS-referenced PTP Grandmaster (IEC/IEEE 61850-9-3 profile): Running `ptpd -2 -s -p /dev/ptp0 -B -H -P -i eth0`: ```text nsh> ptpd -t 5 PTPD (PID 5) status: - clock_source_valid: 1 |- id: 00 14 2d ff fe 61 2b b5 |- utcoffset: 37 |- priority1: 128 |- class: 6 |- accuracy: 34 |- variance: 20061 |- priority2: 128 |- gm_id: 00 14 2d ff fe 61 2b b5 |- stepsremoved: 0 '- timesource: 160 - last_clock_update: 2026-09-17T20:25:40.759091596 - last_delta_ns: -383 - last_adjtime_ns: -80539 - drift_ppb: -82636 - path_delay_ns: 0 ``` Phase locked to **-383 ns** residual error with crystal drift disciplined at **-82636 ppb**. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
