xiaoxiang781216 commented on code in PR #20125: URL: https://github.com/apache/nuttx/pull/20125#discussion_r4104945332
########## arch/risc-v/src/common/riscv_exception_common.S: ########## @@ -223,16 +222,6 @@ return_from_syscall: REGSTORE a0, REG_A0(sp) /* Syscall return value to user context */ -#ifdef CONFIG_RISCV_FRAME_TRACE Review Comment: please remove all related change from pr instead add/remove. ########## arch/risc-v/include/irq.h: ########## @@ -242,7 +242,26 @@ # define REG_INT_CTX_NDX 32 #endif -#ifdef CONFIG_ARCH_RISCV_INTXCPT_EXTREGS +/* On a CLIC part, mcause carries mpp / mpie / mpil / interrupt -- state that + * mret consults -- so it must be saved and restored with the frame, not just + * read for dispatch. It is appended above REG_INT_CTX, so that slot and + * everything below it keep their offsets. + */ + +#if defined(CONFIG_ARCH_CHIP_ESP32P4) && !defined(CONFIG_BUILD_FLAT) Review Comment: it isn't good to check chip symbol in the common header file ########## arch/risc-v/src/common/riscv_exception_common.S: ########## @@ -353,8 +358,14 @@ return_from_exception: csrw CSR_STATUS, s0 #ifdef CONFIG_ARCH_RV_HAVE_CLIC REGLOAD s0, REG_INT_THRESH(sp) /* restore interrupt threshold */ +#ifdef CONFIG_ARCH_RV_CLIC_INTTHRESH_MMIO Review Comment: but CONFIG_ARCH_RV_CLIC_INTTHRESH_MMIO is defined in esp32 specific Kconfig ########## arch/risc-v/src/common/espressif/esp_p4dbg.h: ########## @@ -0,0 +1,99 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_p4dbg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Debug counters for the protected build, CONFIG_ESPRESSIF_P4DBG. + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_P4DBG_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_P4DBG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> + +#ifdef CONFIG_ESPRESSIF_P4DBG +# define P4DBG 1 Review Comment: why not check CONFIG_ESPRESSIF_P4DBG directly ########## arch/risc-v/src/esp32p4/hal_esp32p4.cmake: ########## @@ -461,7 +461,8 @@ list( if(CONFIG_ESPRESSIF_KERNEL_OWNS_PMP) list( - REMOVE_ITEM HAL_SRCS + REMOVE_ITEM Review Comment: merge to the patch which introduce this error ########## arch/risc-v/include/irq.h: ########## @@ -246,9 +246,13 @@ * mret consults -- so it must be saved and restored with the frame, not just * read for dispatch. It is appended above REG_INT_CTX, so that slot and * everything below it keep their offsets. + * + * Only a protected build needs this: a flat build never returns to a lower + * privilege level, so nothing consumes the saved mpp. Keeping the frame at + * its original size there leaves every flat RISC-V target untouched. */ -#if defined(CONFIG_ARCH_CHIP_ESP32P4) && !defined(CONFIG_BUILD_FLAT) +#if defined(CONFIG_ARCH_RV_HAVE_CLIC) && !defined(CONFIG_BUILD_FLAT) Review Comment: merge to the first patch ########## arch/risc-v/include/irq.h: ########## @@ -829,6 +833,75 @@ int up_this_cpu(void); #ifdef CONFIG_ARCH_RV_HAVE_CLIC +#ifdef CONFIG_ARCH_RV_CLIC_INTTHRESH_MMIO + +/**************************************************************************** + * Name: up_irq_save + * + * Description: + * Disable interrupts by setting interrupt threshold to maximum and return + * the previous threshold value. + * + * Some CLIC implementations place the threshold in a memory-mapped + * register rather than in the mintthresh CSR; a chip advertises that by + * defining ARCH_RV_CLIC_INTTHRESH_MMIO. There is no single-instruction + * for such a register, so the read-modify-write runs with STATUS_IE + * cleared to keep it atomic against an interrupt arriving part way + * through, and the write is followed by a read because the core does not + * act on the new threshold until the store has been forced out. + * + ****************************************************************************/ + +noinstrument_function static inline_function irqstate_t up_irq_save(void) +{ + volatile uint32_t *thresh = + (volatile uint32_t *)CONFIG_ARCH_RV_CLIC_INTTHRESH_MMIO; + irqstate_t flags; + uintreg_t status; + + __asm__ __volatile__ + ( + "csrrc %0, " __XSTR(CSR_STATUS) ", %1\n" + : "=r" (status) + : "r"(STATUS_IE) + : "memory" + ); + + flags = *thresh; + *thresh = CONFIG_ARCH_RV_CLIC_INTTHRESH_MMIO_MAX; Review Comment: but CONFIG_ARCH_RV_CLIC_INTTHRESH_MMIO_MAX is defined in esp32 specific Kconfig -- This is an automated message from the Apache Git Service. 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