NevynUK commented on code in PR #20125:
URL: https://github.com/apache/nuttx/pull/20125#discussion_r4144255372
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arch/risc-v/include/irq.h:
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@@ -829,6 +833,75 @@ int up_this_cpu(void);
#ifdef CONFIG_ARCH_RV_HAVE_CLIC
+#ifdef CONFIG_ARCH_RV_CLIC_INTTHRESH_MMIO
+
+/****************************************************************************
+ * Name: up_irq_save
+ *
+ * Description:
+ * Disable interrupts by setting interrupt threshold to maximum and return
+ * the previous threshold value.
+ *
+ * Some CLIC implementations place the threshold in a memory-mapped
+ * register rather than in the mintthresh CSR; a chip advertises that by
+ * defining ARCH_RV_CLIC_INTTHRESH_MMIO. There is no single-instruction
+ * for such a register, so the read-modify-write runs with STATUS_IE
+ * cleared to keep it atomic against an interrupt arriving part way
+ * through, and the write is followed by a read because the core does not
+ * act on the new threshold until the store has been forced out.
+ *
+ ****************************************************************************/
+
+noinstrument_function static inline_function irqstate_t up_irq_save(void)
+{
+ volatile uint32_t *thresh =
+ (volatile uint32_t *)CONFIG_ARCH_RV_CLIC_INTTHRESH_MMIO;
+ irqstate_t flags;
+ uintreg_t status;
+
+ __asm__ __volatile__
+ (
+ "csrrc %0, " __XSTR(CSR_STATUS) ", %1\n"
+ : "=r" (status)
+ : "r"(STATUS_IE)
+ : "memory"
+ );
+
+ flags = *thresh;
+ *thresh = CONFIG_ARCH_RV_CLIC_INTTHRESH_MMIO_MAX;
Review Comment:
Changed.
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