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commit aee40e23486feb27d23fd82d29cf933b8e083b06 Author: Ricardo Maurizio Paul <[email protected]> AuthorDate: Mon Oct 5 14:54:53 2026 +0200 Documentation/stm32h5: note that the ICACHE uses the MPU. The ICACHE driver now maps the OTP, read-only and EDATA flash areas non-cacheable with an MPU region. Say so in the peripheral support table. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Ricardo Maurizio Paul <[email protected]> --- Documentation/platforms/arm/stm32h5/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/platforms/arm/stm32h5/index.rst b/Documentation/platforms/arm/stm32h5/index.rst index 3375b1fae3a..4432d1a0bcf 100644 --- a/Documentation/platforms/arm/stm32h5/index.rst +++ b/Documentation/platforms/arm/stm32h5/index.rst @@ -39,7 +39,7 @@ FDCAN Yes GPDMA Yes GPIO Yes I2C Yes -ICACHE Yes +ICACHE Yes Uses the MPU to keep OTP, RO and EDATA flash uncached. RCC Yes USART Yes LPUART Yes
