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commit 8374dc60bd34e863953fd9963d72e94364a80318 Author: Ricardo Maurizio Paul <[email protected]> AuthorDate: Mon Oct 5 14:44:04 2026 +0200 arch/arm/stm32h5: stop disabling the ICACHE for UID, OTP and EDATA reads. stm32_get_uniqueid() and flash_read_eccsafe16() (OTP and EDATA word reads) disabled the ICACHE around their reads and enabled it again afterwards, so that the read did not go through the ICACHE. The MPU region added by the previous commit makes these areas non-cacheable, so the reads bypass the ICACHE anyway. Remove the disable/enable pairs. Each pair also invalidated the whole ICACHE, and flash_read_eccsafe16() did it with interrupts disabled, twice for every 32-bit OTP read. The MPU is not applied in the HardFault and NMI handlers (HFNMIENA=0), so a UID read from those handlers is no longer protected. Nothing in the tree does that. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Ricardo Maurizio Paul <[email protected]> --- arch/arm/src/common/stm32/stm32_uid.c | 24 ------------------------ arch/arm/src/stm32h5/stm32h563xx_flash.c | 29 +++++------------------------ 2 files changed, 5 insertions(+), 48 deletions(-) diff --git a/arch/arm/src/common/stm32/stm32_uid.c b/arch/arm/src/common/stm32/stm32_uid.c index 016b447d368..e710dabcf64 100644 --- a/arch/arm/src/common/stm32/stm32_uid.c +++ b/arch/arm/src/common/stm32/stm32_uid.c @@ -46,10 +46,6 @@ #include "chip.h" #include "stm32_uid.h" -#ifdef CONFIG_STM32_ICACHE -# include "stm32_icache.h" -#endif - #ifdef STM32_SYSMEM_UID /* Not defined for some STM32 parts */ /**************************************************************************** @@ -60,19 +56,6 @@ void stm32_get_uniqueid(uint8_t uniqueid[12]) { uint32_t uid[3]; int i; -#ifdef CONFIG_STM32_ICACHE - bool icache_enabled; - - /* The UID on STM32 Cortex-M33 parts cannot be read while the instruction - * cache is enabled. Preserve the cache state across the UID access. - */ - - icache_enabled = stm32_icache_enabled(); - if (icache_enabled) - { - stm32_disable_icache(); - } -#endif /* Read the UID with 32-bit accesses. Some parts (STM32H5) store the UID * in flash memory that does not support 8-bit reads. @@ -83,13 +66,6 @@ void stm32_get_uniqueid(uint8_t uniqueid[12]) uid[i] = getreg32(STM32_SYSMEM_UID + 4 * i); } -#ifdef CONFIG_STM32_ICACHE - if (icache_enabled) - { - stm32_enable_icache(); - } -#endif - memcpy(uniqueid, uid, 12); } diff --git a/arch/arm/src/stm32h5/stm32h563xx_flash.c b/arch/arm/src/stm32h5/stm32h563xx_flash.c index ab7a962c4af..4233a13a6d3 100644 --- a/arch/arm/src/stm32h5/stm32h563xx_flash.c +++ b/arch/arm/src/stm32h5/stm32h563xx_flash.c @@ -374,12 +374,11 @@ static void flash_lock_opt(void) * Name: flash_read_eccsafe16 * * Description: - * Read one 16-bit half-word of EDATA or OTP. Both only support 16 and - * 32-bit reads, so the ICACHE, which would fill whole lines, is disabled - * for the read. Reading a blank (erased, never programmed) half-word - * raises the Flash ECC NMI, which is masked in the SBS first and handled - * instead by checking ECCDETR afterwards. Both are restored before - * returning. + * Read one 16-bit half-word of EDATA or OTP. Both areas are mapped + * non-cacheable by the ICACHE driver, so the read bypasses the ICACHE. + * Reading a blank (erased, never programmed) half-word raises the Flash + * ECC NMI, which is masked in the SBS first and handled instead by + * checking ECCDETR afterwards. The mask is restored before returning. * * Input Parameters: * addr - Address of the half-word @@ -398,20 +397,9 @@ static uint16_t flash_read_eccsafe16(uintptr_t addr, uint32_t eccd, irqstate_t flags; uint16_t value; uint32_t eccnmir; -#ifdef CONFIG_STM32_ICACHE - bool icache; -#endif flags = up_irq_save(); -#ifdef CONFIG_STM32_ICACHE - icache = stm32_icache_enabled(); - if (icache) - { - stm32_disable_icache(); - } -#endif - eccnmir = getreg32(STM32_SBS_ECCNMIR); putreg32(eccnmir | SBS_ECCNMIR_ECCNMI_MASK_EN, STM32_SBS_ECCNMIR); @@ -427,13 +415,6 @@ static uint16_t flash_read_eccsafe16(uintptr_t addr, uint32_t eccd, putreg32(eccnmir, STM32_SBS_ECCNMIR); -#ifdef CONFIG_STM32_ICACHE - if (icache) - { - stm32_enable_icache(); - } -#endif - up_irq_restore(flags); return value;
