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commit b55003acf74c3d775309ffd8d80ca4aa8e99e6cb Author: raiden00pl <[email protected]> AuthorDate: Wed Aug 26 11:43:33 2026 +0200 arch/arm/stm32u5: Name the DMA instances STM32_DMA1 and STM32_DMA2 Rename the GPDMA1 and LPDMA1 base addresses to the STM32_DMAx instance naming. Interrupt vector names keep the reference manual names. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/src/stm32u5/hardware/stm32_memorymap.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h index fde84791f9b..f02925bb017 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h @@ -127,7 +127,11 @@ /* AHB1 Base Addresses ******************************************************/ -#define STM32_GPDMA1_BASE 0x40020000 +/* DMA1 is the GPDMA1 instance and DMA2 is the LPDMA1 instance. All + * STM32 DMA instances of the GPDMA/LPDMA IP family are named DMAx. + */ + +#define STM32_DMA1_BASE 0x40020000 #define STM32_CORDIC_BASE 0x40021000 #define STM32_FMAC_BASE 0x40021400 #define STM32_FLASHIF_BASE 0x40022000 @@ -206,6 +210,6 @@ #define STM32_GTZC2_TZIC_BASE 0x46023400 #define STM32_GTZC2_MPCBB4_BASE 0x46023800 #define STM32_ADF1_BASE 0x46024000 -#define STM32_LPDMA1_BASE 0x46025000 +#define STM32_DMA2_BASE 0x46025000 #endif /* __ARCH_ARM_SRC_STM32U5_STM32_MEMORYMAP_H */
