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commit d8f95c01b0d31f3ae61f88496ee5fb0457264a4a Author: raiden00pl <[email protected]> AuthorDate: Wed Oct 21 10:48:02 2026 +0200 arch/arm/src/common/stm32: refuse TIM1 and TIM8 as tickless timer The compare interrupt of the advanced timers is on its own vector, which the tickless driver never attaches, so the interval timer fired only on counter overflow. Reject them at build time like the basic timers. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/src/common/stm32/Kconfig.system | 3 ++- arch/arm/src/common/stm32/stm32_tickless.c | 25 ++++++------------------- 2 files changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/arm/src/common/stm32/Kconfig.system b/arch/arm/src/common/stm32/Kconfig.system index 5a4b85f1b29..a6911efcf7c 100644 --- a/arch/arm/src/common/stm32/Kconfig.system +++ b/arch/arm/src/common/stm32/Kconfig.system @@ -45,7 +45,8 @@ config STM32_TICKLESS_TIMER range 1 17 ---help--- If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. + assigned to provided the timer needed by the OS. The basic timers + TIM6/TIM7 and the advanced timers TIM1/TIM8 are not supported. config STM32_TICKLESS_CHANNEL int "Tickless timer channel" diff --git a/arch/arm/src/common/stm32/stm32_tickless.c b/arch/arm/src/common/stm32/stm32_tickless.c index ae8772a8898..fd6aca02f14 100644 --- a/arch/arm/src/common/stm32/stm32_tickless.c +++ b/arch/arm/src/common/stm32/stm32_tickless.c @@ -121,12 +121,14 @@ # error Basic timers not supported by the tickless driver #endif +#if (CONFIG_STM32_TICKLESS_TIMER == 1) || \ + (CONFIG_STM32_TICKLESS_TIMER == 8) +# error Advanced timers not supported by the tickless driver +#endif + /* Debug MCU freeze bit of the tickless timer */ -#if CONFIG_STM32_TICKLESS_TIMER == 1 && defined(DBGMCU_TIM1_STOP) -# define TICKLESS_DBGMCU_FZ STM32_DBGMCU_TIM1_FZ -# define TICKLESS_DBGMCU_STOP DBGMCU_TIM1_STOP -#elif CONFIG_STM32_TICKLESS_TIMER == 2 && defined(DBGMCU_TIM2_STOP) +#if CONFIG_STM32_TICKLESS_TIMER == 2 && defined(DBGMCU_TIM2_STOP) # define TICKLESS_DBGMCU_FZ STM32_DBGMCU_TIM2_FZ # define TICKLESS_DBGMCU_STOP DBGMCU_TIM2_STOP #elif CONFIG_STM32_TICKLESS_TIMER == 3 && defined(DBGMCU_TIM3_STOP) @@ -138,9 +140,6 @@ #elif CONFIG_STM32_TICKLESS_TIMER == 5 && defined(DBGMCU_TIM5_STOP) # define TICKLESS_DBGMCU_FZ STM32_DBGMCU_TIM5_FZ # define TICKLESS_DBGMCU_STOP DBGMCU_TIM5_STOP -#elif CONFIG_STM32_TICKLESS_TIMER == 8 && defined(DBGMCU_TIM8_STOP) -# define TICKLESS_DBGMCU_FZ STM32_DBGMCU_TIM8_FZ -# define TICKLESS_DBGMCU_STOP DBGMCU_TIM8_STOP #elif CONFIG_STM32_TICKLESS_TIMER == 9 && defined(DBGMCU_TIM9_STOP) # define TICKLESS_DBGMCU_FZ STM32_DBGMCU_TIM9_FZ # define TICKLESS_DBGMCU_STOP DBGMCU_TIM9_STOP @@ -486,12 +485,6 @@ void up_timer_initialize(void) { switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32_TIM1 - case 1: - g_tickless.base = STM32_TIM1_BASE; - break; -#endif - #ifdef CONFIG_STM32_TIM2 case 2: g_tickless.base = STM32_TIM2_BASE; @@ -515,12 +508,6 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32_TIM8 - case 8: - g_tickless.base = STM32_TIM8_BASE; - break; -#endif - #ifdef CONFIG_STM32_TIM9 case 9: g_tickless.base = STM32_TIM9_BASE;
