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commit 87a156e93c76d7e4dc0141b4479e04bb7a64b4fe Author: raiden00pl <[email protected]> AuthorDate: Sat Oct 10 20:33:56 2026 +0200 !arch/arm/src/common/stm32: unify SysTick timer driver Use one common SysTick timer driver for all ARMv7-M and ARMv8-M STM32 families and remove the STM32F7, STM32H7, STM32L4, STM32N6, STM32WB, STM32WL5 and Cortex-M33 copies. The SysTick clock source is selected in Kconfig: the CPU clock (the default on all families) or the HCLK/8 external reference. The CPU clock differs from HCLK on STM32H7 and STM32N6, where the board must define STM32_CPUCLK_FREQUENCY. The SysTick current value is cleared at init as the STM32F7 and STM32H7 copies did. The families that had their own copy gain up_adjtime() and the SysTick lower-half (CONFIG_ARMV7M_SYSTICK/CONFIG_ARMV8M_SYSTICK with CONFIG_TIMER_ARCH). BREAKING CHANGE: the STM32F7 SysTick default changes from HCLK/8 to the CPU clock, as on all other families. The tick rate does not change, but the longest possible tick is 8 times shorter. STM32F7 configurations that need the old clock select CONFIG_STM32_SYSTICK_HCLK_DIV8. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- .github/CODEOWNERS | 8 +- arch/arm/src/common/stm32/CMakeLists.txt | 22 ++- arch/arm/src/common/stm32/Kconfig.system | 18 +++ arch/arm/src/common/stm32/Make.defs | 23 +-- arch/arm/src/common/stm32/stm32_systick.h | 58 +++++++ .../{stm32_timerisr_armv7m.c => stm32_timerisr.c} | 54 +++---- arch/arm/src/common/stm32/stm32_timerisr_m33_v1.c | 125 --------------- arch/arm/src/stm32f7/CMakeLists.txt | 4 +- arch/arm/src/stm32f7/Make.defs | 4 +- arch/arm/src/stm32f7/stm32_timerisr.c | 142 ----------------- arch/arm/src/stm32h7/CMakeLists.txt | 2 - arch/arm/src/stm32h7/Make.defs | 2 - arch/arm/src/stm32h7/stm32_timerisr.c | 168 --------------------- arch/arm/src/stm32l4/CMakeLists.txt | 4 +- arch/arm/src/stm32l4/Make.defs | 4 +- arch/arm/src/stm32l4/stm32l4_timerisr.c | 147 ------------------ arch/arm/src/stm32n6/CMakeLists.txt | 3 +- arch/arm/src/stm32n6/Make.defs | 2 +- arch/arm/src/stm32n6/stm32_timerisr.c | 116 -------------- arch/arm/src/stm32wb/CMakeLists.txt | 4 +- arch/arm/src/stm32wb/Make.defs | 4 +- arch/arm/src/stm32wb/stm32wb_timerisr.c | 148 ------------------ arch/arm/src/stm32wl5/CMakeLists.txt | 1 - arch/arm/src/stm32wl5/Make.defs | 2 +- arch/arm/src/stm32wl5/stm32wl5_timerisr.c | 151 ------------------ 25 files changed, 124 insertions(+), 1092 deletions(-) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 41c1464d4af..6c8c05ae783 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -1850,13 +1850,14 @@ arch/arm/src/common/stm32/stm32_start.h [email protected] [email protected] arch/arm/src/common/stm32/stm32_start_m0_v1.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_start_m3m4_v1.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_syscfg.h [email protected] [email protected] [email protected] [email protected] [email protected] +arch/arm/src/common/stm32/stm32_systick.h [email protected] arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_tim.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_tim.h [email protected] [email protected] arch/arm/src/common/stm32/stm32_tim_clk.h [email protected] arch/arm/src/common/stm32/stm32_tim_lowerhalf.c [email protected] [email protected] [email protected] [email protected] [email protected] +arch/arm/src/common/stm32/stm32_timerisr.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_timerisr_armv6m.c [email protected] [email protected] [email protected] [email protected] [email protected] -arch/arm/src/common/stm32/stm32_timerisr_armv7m.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_uart.h [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_uart_m0_v1.h [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h [email protected] [email protected] [email protected] [email protected] [email protected] @@ -4006,7 +4007,6 @@ arch/arm/src/stm32f7/stm32_spi.h [email protected] arch/arm/src/stm32f7/stm32_start.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32f7/stm32_start.h [email protected] [email protected] [email protected] arch/arm/src/stm32f7/stm32_tickless.c [email protected] [email protected] [email protected] [email protected] [email protected] -arch/arm/src/stm32f7/stm32_timerisr.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32f7/stm32_uart.h [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32f7/stm32_uid.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32f7/stm32_uid.h [email protected] [email protected] [email protected] [email protected] @@ -4255,7 +4255,6 @@ arch/arm/src/stm32h7/stm32_spi_slave.c [email protected] alin.jerpelea@so arch/arm/src/stm32h7/stm32_start.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32h7/stm32_start.h [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32h7/stm32_tickless.c [email protected] [email protected] [email protected] [email protected] [email protected] -arch/arm/src/stm32h7/stm32_timerisr.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32h7/stm32_uart.h [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32h7/stm32_uid.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32h7/stm32_uid.h [email protected] [email protected] [email protected] @@ -4423,7 +4422,6 @@ arch/arm/src/stm32l4/stm32l4_spi.h [email protected] [email protected] x arch/arm/src/stm32l4/stm32l4_start.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32l4/stm32l4_start.h [email protected] [email protected] arch/arm/src/stm32l4/stm32l4_tickless.c [email protected] [email protected] [email protected] [email protected] -arch/arm/src/stm32l4/stm32l4_timerisr.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32l4/stm32l4_uart.h [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32l4/stm32l4_uid.c [email protected] [email protected] arch/arm/src/stm32l4/stm32l4_uid.h [email protected] [email protected] @@ -4614,7 +4612,6 @@ arch/arm/src/stm32wb/stm32wb_spi.h [email protected] [email protected] arch/arm/src/stm32wb/stm32wb_start.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32wb/stm32wb_start.h [email protected] [email protected] arch/arm/src/stm32wb/stm32wb_tickless.c [email protected] [email protected] [email protected] [email protected] -arch/arm/src/stm32wb/stm32wb_timerisr.c [email protected] [email protected] arch/arm/src/stm32wb/stm32wb_uart.h [email protected] [email protected] arch/arm/src/stm32wb/stm32wb_uid.c [email protected] [email protected] arch/arm/src/stm32wb/stm32wb_uid.h [email protected] [email protected] @@ -4661,7 +4658,6 @@ arch/arm/src/stm32wl5/stm32wl5_spi.c 49699333+dependabot[bot]@users.noreply.gith arch/arm/src/stm32wl5/stm32wl5_spi.h 49699333+dependabot[bot]@users.noreply.github.com [email protected] arch/arm/src/stm32wl5/stm32wl5_start.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32wl5/stm32wl5_start.h [email protected] [email protected] -arch/arm/src/stm32wl5/stm32wl5_timerisr.c [email protected] [email protected] [email protected] arch/arm/src/stm32wl5/stm32wl5_uart.h [email protected] [email protected] arch/arm/src/stm32wl5/stm32wl5_uid.c [email protected] [email protected] arch/arm/src/stm32wl5/stm32wl5_uid.h [email protected] [email protected] diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 057706e5b21..76c07308640 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -35,6 +35,14 @@ list(APPEND SRCS stm32_waste.c) list(APPEND SRCS stm32_uid.c) list(APPEND SRCS stm32_lsi.c) +if(NOT CONFIG_SCHED_TICKLESS) + if(CONFIG_ARCH_ARMV6M) + list(APPEND SRCS stm32_timerisr_armv6m.c) + else() + list(APPEND SRCS stm32_timerisr.c) + endif() +endif() + if(CONFIG_STM32_IWDG) list(APPEND SRCS stm32_iwdg.c) endif() @@ -66,7 +74,7 @@ endif() if(CONFIG_STM32_COMMON_M33) list(APPEND SRCS stm32_allocateheap_m33_v1.c stm32_irq_m33_v1.c - stm32_start_m33_v1.c stm32_timerisr_m33_v1.c) + stm32_start_m33_v1.c) if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle_m33_v1.c) @@ -164,10 +172,6 @@ if(CONFIG_STM32_COMMON_LEGACY) if(CONFIG_STM32_TICKLESS_TIMER) list(APPEND SRCS stm32_tickless_m3m4_v1.c) - elseif(CONFIG_ARCH_ARMV6M) - list(APPEND SRCS stm32_timerisr_armv6m.c) - else() - list(APPEND SRCS stm32_timerisr_armv7m.c) endif() if(CONFIG_BUILD_PROTECTED) @@ -406,14 +410,6 @@ if(CONFIG_ARCH_CORTEXM0) list(APPEND SRCS stm32_idle_m0_v1.c) endif() - if(NOT CONFIG_SCHED_TICKLESS) - if(CONFIG_ARCH_ARMV6M) - list(APPEND SRCS stm32_timerisr_armv6m.c) - else() - list(APPEND SRCS stm32_timerisr_armv7m.c) - endif() - endif() - if(CONFIG_STM32_PWR) if(CONFIG_STM32_HAVE_IP_PWR_M0_V1) list(APPEND SRCS stm32_pwr_m0_v1.c) diff --git a/arch/arm/src/common/stm32/Kconfig.system b/arch/arm/src/common/stm32/Kconfig.system index e21bbdc7706..67586e410aa 100644 --- a/arch/arm/src/common/stm32/Kconfig.system +++ b/arch/arm/src/common/stm32/Kconfig.system @@ -82,6 +82,24 @@ config STM32_SYSTICK_CORECLK_DIV16 endchoice +choice + prompt "SysTick clock source" + depends on ARCH_ARMV7M || ARCH_ARMV8M + default STM32_SYSTICK_CPUCLK + +config STM32_SYSTICK_CPUCLK + bool "CPU clock" + +config STM32_SYSTICK_HCLK_DIV8 + bool "HCLK divided by 8" + depends on !ARCH_CHIP_STM32H7 && !ARCH_CHIP_STM32N6 + ---help--- + SysTick external reference clock. Not offered on STM32H7, where + on silicon revision Y the external clock is not divided by 8 + (ES0392 erratum 2.2.3), and on STM32N6, where it is not verified. + +endchoice + config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG bool "Custom clock configuration" default n diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index 41a28d50ff5..e04f277f0e8 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -43,6 +43,14 @@ CHIP_CSRCS += stm32_waste.c CHIP_CSRCS += stm32_uid.c CHIP_CSRCS += stm32_lsi.c +ifneq ($(CONFIG_SCHED_TICKLESS),y) +ifeq ($(CONFIG_ARCH_ARMV6M),y) +CHIP_CSRCS += stm32_timerisr_armv6m.c +else +CHIP_CSRCS += stm32_timerisr.c +endif +endif + ifeq ($(CONFIG_STM32_IWDG),y) CHIP_CSRCS += stm32_iwdg.c endif @@ -79,7 +87,6 @@ ifeq ($(CONFIG_STM32_COMMON_M33),y) CHIP_CSRCS += stm32_allocateheap_m33_v1.c CHIP_CSRCS += stm32_irq_m33_v1.c CHIP_CSRCS += stm32_start_m33_v1.c -CHIP_CSRCS += stm32_timerisr_m33_v1.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle_m33_v1.c endif @@ -165,12 +172,6 @@ endif ifdef CONFIG_STM32_TICKLESS_TIMER CHIP_CSRCS += stm32_tickless_m3m4_v1.c -else -ifeq ($(CONFIG_ARCH_ARMV6M),y) -CHIP_CSRCS += stm32_timerisr_armv6m.c -else -CHIP_CSRCS += stm32_timerisr_armv7m.c -endif endif ifeq ($(CONFIG_BUILD_PROTECTED),y) @@ -461,14 +462,6 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle_m0_v1.c endif -ifneq ($(CONFIG_SCHED_TICKLESS),y) -ifeq ($(CONFIG_ARCH_ARMV6M),y) -CHIP_CSRCS += stm32_timerisr_armv6m.c -else -CHIP_CSRCS += stm32_timerisr_armv7m.c -endif -endif - ifeq ($(CONFIG_STM32_PWR),y) ifeq ($(CONFIG_STM32_HAVE_IP_PWR_M0_V1),y) CHIP_CSRCS += stm32_pwr_m0_v1.c diff --git a/arch/arm/src/common/stm32/stm32_systick.h b/arch/arm/src/common/stm32/stm32_systick.h new file mode 100644 index 00000000000..77efe351d9a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_systick.h @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_systick.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSTICK_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSTICK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> + +#include <arch/board/board.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SysTick clock: the CPU clock (CLKSOURCE = 1) or the HCLK/8 external + * reference (CLKSOURCE = 0). The CPU clock differs from HCLK on STM32H7 + * and STM32N6, where the board must define STM32_CPUCLK_FREQUENCY. + */ + +#if defined(CONFIG_STM32_SYSTICK_HCLK_DIV8) +# define STM32_SYSTICK_CORECLK false +# define STM32_SYSTICK_CLOCK (STM32_HCLK_FREQUENCY / 8) +#elif defined(STM32_CPUCLK_FREQUENCY) +# define STM32_SYSTICK_CORECLK true +# define STM32_SYSTICK_CLOCK STM32_CPUCLK_FREQUENCY +#elif defined(CONFIG_ARCH_CHIP_STM32H7) || defined(CONFIG_ARCH_CHIP_STM32N6) +# error "board.h must define STM32_CPUCLK_FREQUENCY" +#else +# define STM32_SYSTICK_CORECLK true +# define STM32_SYSTICK_CLOCK STM32_HCLK_FREQUENCY +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSTICK_H */ diff --git a/arch/arm/src/common/stm32/stm32_timerisr_armv7m.c b/arch/arm/src/common/stm32/stm32_timerisr.c similarity index 78% rename from arch/arm/src/common/stm32/stm32_timerisr_armv7m.c rename to arch/arm/src/common/stm32/stm32_timerisr.c index b7f8e713252..6945a5d5fe7 100644 --- a/arch/arm/src/common/stm32/stm32_timerisr_armv7m.c +++ b/arch/arm/src/common/stm32/stm32_timerisr.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_timerisr_armv7m.c + * arch/arm/src/common/stm32/stm32_timerisr.c * * SPDX-License-Identifier: Apache-2.0 * @@ -40,7 +40,7 @@ #include "systick.h" #include "chip.h" -#include "stm32.h" +#include "stm32_systick.h" /**************************************************************************** * Pre-processor Definitions @@ -50,23 +50,9 @@ * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of * system clock ticks per second. That value is a user configurable setting * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK) - * divided by 8. The SysTick can work either with this clock or with the - * Cortex clock (HCLK), configurable in the SysTick Control and Status - * register. */ -#undef CONFIG_STM32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */ - /* And I don't know now to re-configure it yet */ - -#ifdef CONFIG_STM32_SYSTICK_HCLKd8 -# define SYSTICK_CLOCK (STM32_HCLK_FREQUENCY / 8) -#else -# define SYSTICK_CLOCK (STM32_HCLK_FREQUENCY) -#endif - -#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1) +#define SYSTICK_RELOAD ((STM32_SYSTICK_CLOCK / CLK_TCK) - 1) /* The size of the reload field is 24 bits. Verify that the reload value * will fit in the reload register. @@ -77,6 +63,11 @@ # error SYSTICK_RELOAD exceeds the range of the RELOAD register #endif +#if (defined(CONFIG_ARMV7M_SYSTICK) || defined(CONFIG_ARMV8M_SYSTICK)) && \ + defined(CONFIG_TIMER_ARCH) +# define HAVE_SYSTICK_LOWERHALF 1 +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -90,7 +81,7 @@ * ****************************************************************************/ -#if !defined(CONFIG_ARMV7M_SYSTICK) && !defined(CONFIG_TIMER_ARCH) +#ifndef HAVE_SYSTICK_LOWERHALF static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -161,24 +152,14 @@ void up_timer_initialize(void) regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); putreg32(regval, NVIC_SYSH12_15_PRIORITY); - /* Make sure that the SYSTICK clock source is set correctly */ - -#if 0 /* Does not work. Comes up with HCLK source and I can't change it */ - regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32_SYSTICK_HCLKd8 - regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; -#else - regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; -#endif - putreg32(regval, NVIC_SYSTICK_CTRL); -#endif - -#if defined(CONFIG_ARMV7M_SYSTICK) && defined(CONFIG_TIMER_ARCH) - up_timer_set_lowerhalf(systick_initialize(true, STM32_HCLK_FREQUENCY, -1)); +#ifdef HAVE_SYSTICK_LOWERHALF + up_timer_set_lowerhalf(systick_initialize(STM32_SYSTICK_CORECLK, + STM32_SYSTICK_CLOCK, -1)); #else /* Configure SysTick to interrupt at the requested rate */ putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + putreg32(0, NVIC_SYSTICK_CURRENT); /* Attach the timer interrupt vector */ @@ -186,8 +167,13 @@ void up_timer_initialize(void) /* Enable SysTick interrupts */ - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | - NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + regval = NVIC_SYSTICK_CTRL_TICKINT | NVIC_SYSTICK_CTRL_ENABLE; + if (STM32_SYSTICK_CORECLK) + { + regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; + } + + putreg32(regval, NVIC_SYSTICK_CTRL); /* And enable the timer interrupt */ diff --git a/arch/arm/src/common/stm32/stm32_timerisr_m33_v1.c b/arch/arm/src/common/stm32/stm32_timerisr_m33_v1.c deleted file mode 100644 index 5c8a83586a0..00000000000 --- a/arch/arm/src/common/stm32/stm32_timerisr_m33_v1.c +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_timerisr_m33_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include <stdint.h> -#include <time.h> - -#include <nuttx/debug.h> -#include <nuttx/arch.h> -#include <arch/board/board.h> - -#include "nvic.h" -#include "clock/clock.h" -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * The Cortex System Timer (SysTick) uses the Cortex clock (HCLK). - */ - -#define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) - -/* The size of the reload field is 24 bits. Verify that the reload value - * will fit in the reload register. - */ - -#if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -static int stm32_timerisr(int irq, uint32_t *regs, void *arg) -{ - /* Process timer interrupt */ - - nxsched_process_timer(); - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - uint32_t regval; - - /* Set the SysTick interrupt to the default priority */ - - regval = getreg32(NVIC_SYSH12_15_PRIORITY); - regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; - regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); - putreg32(regval, NVIC_SYSH12_15_PRIORITY); - - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); - - /* Attach the timer interrupt vector */ - - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); - - /* Enable SysTick interrupts */ - - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | - NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); - - /* And enable the timer interrupt */ - - up_enable_irq(STM32_IRQ_SYSTICK); -} diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index 53178af169b..2d0798008fc 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -35,10 +35,8 @@ list( stm32_start.c stm32_capture.c) -if(CONFIG_STM32_TICKLESS_TIMER) +if(CONFIG_SCHED_TICKLESS) list(APPEND SRCS stm32_tickless.c) -else() - list(APPEND SRCS stm32_timerisr.c) endif() if(CONFIG_STM32_PROGMEM) diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index aa7cec2c8e8..bbfc6526cd3 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -34,9 +34,7 @@ CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c CHIP_CSRCS += stm32_start.c stm32_capture.c -ifneq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += stm32_timerisr.c -else +ifeq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32_tickless.c endif diff --git a/arch/arm/src/stm32f7/stm32_timerisr.c b/arch/arm/src/stm32f7/stm32_timerisr.c deleted file mode 100644 index 637b31bd0f6..00000000000 --- a/arch/arm/src/stm32f7/stm32_timerisr.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_timerisr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include <stdint.h> -#include <time.h> - -#include <nuttx/debug.h> -#include <nuttx/arch.h> -#include <arch/board/board.h> - -#include "nvic.h" -#include "clock/clock.h" -#include "arm_internal.h" -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Select MCU-specific settings - * - * The RCC feeds the external clock of the Cortex System Timer (SysTick) with - * the AHB clock (HCLK) divided by 8. The SysTick can work either with this - * clock or with the Cortex clock (HCLK), configurable in the SysTick control - * and status register. - * - * The SysTick calibration value is fixed to 18750, which gives a reference - * time base of 1 ms with the SysTick clock set to 18.75 MHz (HCLK/8, with - * HCLK set to 150 MHz). - */ - -#define STM32_SYSTICK_CLOCK (STM32_HCLK_FREQUENCY / 8) - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * For example, suppose HCLK = 216 MHz and CLK_TCK = 100, then: - * - * STM32_SYSTICK_CLOCK = 216 MHz / 8 = 27 MHz - * SYSTICK_RELOAD = (27,000,000 / 100) - 1 = 269,999 - */ - -#define SYSTICK_RELOAD ((STM32_SYSTICK_CLOCK / CLK_TCK) - 1) - -/* The size of the reload field is 24 bits. Verify that the reload value - * will fit in the reload register. - */ - -#if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -static int stm32_timerisr(int irq, uint32_t *regs, void *arg) -{ - /* Process timer interrupt */ - - nxsched_process_timer(); - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize the timer - * interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - uint32_t regval; - - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); - putreg32(0, NVIC_SYSTICK_CURRENT); - - /* Attach the timer interrupt vector */ - - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); - - /* Enable SysTick interrupts: - * - * NVIC_SYSTICK_CTRL_CLKSOURCE=0 : Use the implementation defined clock - * source which, for the STM32F7, will be - * HCLK/8 - * NVIC_SYSTICK_CTRL_TICKINT=1 : Generate interrupts - * NVIC_SYSTICK_CTRL_ENABLE : Enable the counter - */ - - regval = (NVIC_SYSTICK_CTRL_TICKINT | NVIC_SYSTICK_CTRL_ENABLE); - putreg32(regval, NVIC_SYSTICK_CTRL); - - /* And enable the timer interrupt */ - - up_enable_irq(STM32_IRQ_SYSTICK); -} diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index 8ff834153bf..3bd84e3bbc8 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -52,8 +52,6 @@ endif() if(CONFIG_SCHED_TICKLESS) list(APPEND SRCS stm32_tickless.c) -else() - list(APPEND SRCS stm32_timerisr.c) endif() if(CONFIG_ARM_MPU) diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 66c2b6b96db..37a65e6d9a3 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -51,8 +51,6 @@ CHIP_CSRCS += stm32_start.c stm32_rcc.c stm32_lowputc.c stm32_serial.c ifeq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32_tickless.c -else -CHIP_CSRCS += stm32_timerisr.c endif ifeq ($(CONFIG_ARM_MPU),y) diff --git a/arch/arm/src/stm32h7/stm32_timerisr.c b/arch/arm/src/stm32h7/stm32_timerisr.c deleted file mode 100644 index e5bd4cf0515..00000000000 --- a/arch/arm/src/stm32h7/stm32_timerisr.c +++ /dev/null @@ -1,168 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_timerisr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include <stdint.h> -#include <time.h> - -#include <nuttx/debug.h> -#include <nuttx/arch.h> -#include <arch/board/board.h> - -#include "nvic.h" -#include "clock/clock.h" -#include "arm_internal.h" -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Select MCU-specific settings - * - * The RCC feeds the external clock of the Cortex System Timer (SysTick) with - * the AHB clock (HCLK) divided by 8. The SysTick can work either with this - * clock or with the Cortex clock (HCLK), configurable in the SysTick control - * and status register. - * - * The SysTick calibration value is fixed to 18750, which gives a reference - * time base of 1 ms with the SysTick clock set to 18.75 MHz (HCLK/8, with - * HCLK set to 150 MHz). - * - * REVISIT: Per ES0392 Rev 4: STM32H743xI Errata sheet STM32H743xI device - * limitations - * - * SysTick external clock is not HCLK/8 - * Description - * The SysTick external clock is the system clock, instead of the system - * clock divided by 8 (HCLK/8). - * Workaround - * Use the system clock (HCLK) as external clock and multiply the reload - * value by 8 in STK_LOAD register (take care that the maximum value is - * 224-1). - */ - -#undef CONFIG_STM32_SYSTICK_HCLKd8 - -/* REVISIT: - * It looks like SYSTICK for H7 is always clocked from CPUCLK and doesn't - * depend on the SYSTICK_CTRL_CLKSOURCE bit settings. - */ - -#ifdef CONFIG_STM32_SYSTICK_HCLKd8 -# define STM32_SYSTICK_CLOCK (STM32_HCLK_FREQUENCY / 8) -#else -# define STM32_SYSTICK_CLOCK (STM32_CPUCLK_FREQUENCY) -#endif - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * For example, suppose HCLK = 216 MHz and CLK_TCK = 100, then: - * - * STM32_SYSTICK_CLOCK = 216 MHz / 8 = 27 MHz - * SYSTICK_RELOAD = (27,000,000 / 100) - 1 = 269,999 - */ - -#define SYSTICK_RELOAD ((STM32_SYSTICK_CLOCK / CLK_TCK) - 1) - -/* The size of the reload field is 24 bits. Verify that the reload value - * will fit in the reload register. - */ - -#if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -static int stm32_timerisr(int irq, uint32_t *regs, void *arg) -{ - /* Process timer interrupt */ - - nxsched_process_timer(); - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize the timer - * interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - uint32_t regval; - - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); - putreg32(0, NVIC_SYSTICK_CURRENT); - - /* Attach the timer interrupt vector */ - - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); - - /* Enable SysTick interrupts: - * - * NVIC_SYSTICK_CTRL_CLKSOURCE : Configurable, 0=HCLK/8, 1=CPU - * NVIC_SYSTICK_CTRL_TICKINT=1 : Generate interrupts - * NVIC_SYSTICK_CTRL_ENABLE : Enable the counter - */ - - regval = (NVIC_SYSTICK_CTRL_TICKINT | NVIC_SYSTICK_CTRL_ENABLE); -#ifndef CONFIG_STM32_SYSTICK_HCLKd8 - regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; -#else - regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; -#endif - putreg32(regval, NVIC_SYSTICK_CTRL); - - /* And enable the timer interrupt */ - - up_enable_irq(STM32_IRQ_SYSTICK); -} diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index cfcedd6ad45..a851827960c 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -44,9 +44,7 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32l4_idle.c) endif() -if(NOT CONFIG_SCHED_TICKLESS) - list(APPEND SRCS stm32l4_timerisr.c) -else() +if(CONFIG_SCHED_TICKLESS) list(APPEND SRCS stm32l4_tickless.c) endif() diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 2df41b48e33..39081676073 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -41,9 +41,7 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32l4_idle.c endif -ifneq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += stm32l4_timerisr.c -else +ifeq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32l4_tickless.c endif diff --git a/arch/arm/src/stm32l4/stm32l4_timerisr.c b/arch/arm/src/stm32l4/stm32l4_timerisr.c deleted file mode 100644 index 2c2b0747a38..00000000000 --- a/arch/arm/src/stm32l4/stm32l4_timerisr.c +++ /dev/null @@ -1,147 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_timerisr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include <stdint.h> -#include <time.h> - -#include <nuttx/debug.h> -#include <nuttx/arch.h> -#include <arch/board/board.h> - -#include "nvic.h" -#include "clock/clock.h" -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK) - * divided by 8. The SysTick can work either with this clock or with the - * Cortex clock (HCLK), configurable in the SysTick Control and Status - * register. - */ - -#undef CONFIG_STM32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */ - /* And I don't know now to re-configure it yet */ - -#ifdef CONFIG_STM32_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) -#else -# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) -#endif - -/* The size of the reload field is 24 bits. Verify that the reload value - * will fit in the reload register. - */ - -#if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -static int stm32_timerisr(int irq, uint32_t *regs, void *arg) -{ - /* Process timer interrupt */ - - nxsched_process_timer(); - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - uint32_t regval; - - /* Set the SysTick interrupt to the default priority */ - - regval = getreg32(NVIC_SYSH12_15_PRIORITY); - regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; - regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); - putreg32(regval, NVIC_SYSH12_15_PRIORITY); - - /* Make sure that the SYSTICK clock source is set correctly */ - -#if 0 /* Does not work. Comes up with HCLK source and I can't change it */ - regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32_SYSTICK_HCLKd8 - regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; -#else - regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; -#endif - putreg32(regval, NVIC_SYSTICK_CTRL); -#endif - - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); - - /* Attach the timer interrupt vector */ - - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); - - /* Enable SysTick interrupts */ - - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | - NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); - - /* And enable the timer interrupt */ - - up_enable_irq(STM32_IRQ_SYSTICK); -} diff --git a/arch/arm/src/stm32n6/CMakeLists.txt b/arch/arm/src/stm32n6/CMakeLists.txt index 983b67744f9..82b0ad67811 100644 --- a/arch/arm/src/stm32n6/CMakeLists.txt +++ b/arch/arm/src/stm32n6/CMakeLists.txt @@ -34,8 +34,7 @@ list( stm32_lowputc.c stm32_rcc.c stm32_start.c - stm32_pwr.c - stm32_timerisr.c) + stm32_pwr.c) if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle.c) diff --git a/arch/arm/src/stm32n6/Make.defs b/arch/arm/src/stm32n6/Make.defs index 9550e4e64a5..6762cedcf5b 100644 --- a/arch/arm/src/stm32n6/Make.defs +++ b/arch/arm/src/stm32n6/Make.defs @@ -33,7 +33,7 @@ include common/stm32/Make.defs # Required STM32N6 files CHIP_CSRCS += stm32_gpio.c stm32_irq.c stm32_lowputc.c stm32_rcc.c -CHIP_CSRCS += stm32_start.c stm32_pwr.c stm32_timerisr.c +CHIP_CSRCS += stm32_start.c stm32_pwr.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c diff --git a/arch/arm/src/stm32n6/stm32_timerisr.c b/arch/arm/src/stm32n6/stm32_timerisr.c deleted file mode 100644 index 5ee494573d6..00000000000 --- a/arch/arm/src/stm32n6/stm32_timerisr.c +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32n6/stm32_timerisr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include <stdint.h> -#include <time.h> - -#include <nuttx/arch.h> -#include <arch/board/board.h> - -#include "nvic.h" -#include "clock/clock.h" -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 ms interval). - * - * SysTick is clocked from the processor clock when CLKSOURCE=1 (the - * configuration used here). The reload value must fit in 24 bits. - */ - -#define SYSTICK_RELOAD ((STM32_CPUCLK_FREQUENCY / CLK_TCK) - 1) - -#if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_timerisr - * - * Description: - * SysTick interrupt handler. Processes the system timer tick. - * - ****************************************************************************/ - -static int stm32_timerisr(int irq, uint32_t *regs, void *arg) -{ - nxsched_process_timer(); - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize the system - * timer interrupt using SysTick clocked from the processor clock. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - uint32_t regval; - - /* Set the SysTick interrupt to the default priority */ - - regval = getreg32(NVIC_SYSH12_15_PRIORITY); - regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; - regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); - putreg32(regval, NVIC_SYSH12_15_PRIORITY); - - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); - - /* Attach the timer interrupt vector */ - - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); - - /* Enable SysTick clocked from the processor clock with interrupts on */ - - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | - NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); - - up_enable_irq(STM32_IRQ_SYSTICK); -} diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index 37e7e6b2317..41b85160b7a 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -41,9 +41,7 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32wb_idle.c) endif() -if(NOT CONFIG_SCHED_TICKLESS) - list(APPEND SRCS stm32wb_timerisr.c) -else() +if(CONFIG_SCHED_TICKLESS) list(APPEND SRCS stm32wb_tickless.c) endif() diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index e57486001ad..2cbdb9d7fe6 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -41,9 +41,7 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32wb_idle.c endif -ifneq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += stm32wb_timerisr.c -else +ifeq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32wb_tickless.c endif diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c deleted file mode 100644 index ea28a500667..00000000000 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ /dev/null @@ -1,148 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_timerisr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include <stdint.h> -#include <time.h> -#include <nuttx/debug.h> - -#include <arch/board/board.h> - -#include "arm_internal.h" -#include "chip.h" -#include "nvic.h" -#include "clock/clock.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK) - * divided by 8. The SysTick can work either with this clock or with the - * Cortex clock (HCLK), configurable in the SysTick Control and Status - * register. - */ - -/* Power up default is HCLK, not HCLK/8. - * And I don't know now to re-configure it yet - */ - -#undef CONFIG_STM32_SYSTICK_HCLKd8 - -#ifdef CONFIG_STM32_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) -#else -# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) -#endif - -/* The size of the reload field is 24 bits. Verify that the reload value - * will fit in the reload register. - */ - -#if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -static int stm32_timerisr(int irq, uint32_t *regs, void *arg) -{ - /* Process timer interrupt */ - - nxsched_process_timer(); - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - uint32_t regval; - - /* Set the SysTick interrupt to the default priority */ - - regval = getreg32(NVIC_SYSH12_15_PRIORITY); - regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; - regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); - putreg32(regval, NVIC_SYSH12_15_PRIORITY); - - /* Make sure that the SYSTICK clock source is set correctly */ - -#if 0 /* Does not work. Comes up with HCLK source and I can't change it */ - regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32_SYSTICK_HCLKd8 - regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; -#else - regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; -#endif - putreg32(regval, NVIC_SYSTICK_CTRL); -#endif - - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); - - /* Attach the timer interrupt vector */ - - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); - - /* Enable SysTick interrupts */ - - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | - NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); - - /* And enable the timer interrupt */ - - up_enable_irq(STM32_IRQ_SYSTICK); -} diff --git a/arch/arm/src/stm32wl5/CMakeLists.txt b/arch/arm/src/stm32wl5/CMakeLists.txt index 2fc5af18c59..b199e8531e0 100644 --- a/arch/arm/src/stm32wl5/CMakeLists.txt +++ b/arch/arm/src/stm32wl5/CMakeLists.txt @@ -35,7 +35,6 @@ set(SRCS stm32wl5_idle.c stm32wl5_pwr.c stm32wl5_flash.c - stm32wl5_timerisr.c stm32wl5_spi.c) if(CONFIG_STM32_IPCC) diff --git a/arch/arm/src/stm32wl5/Make.defs b/arch/arm/src/stm32wl5/Make.defs index d38f6c0ae48..2dac084b034 100644 --- a/arch/arm/src/stm32wl5/Make.defs +++ b/arch/arm/src/stm32wl5/Make.defs @@ -34,7 +34,7 @@ CHIP_CSRCS += stm32wl5_allocateheap.c stm32wl5_exti_gpio.c stm32wl5_gpio.c CHIP_CSRCS += stm32wl5_irq.c stm32wl5_lowputc.c stm32wl5_rcc.c CHIP_CSRCS += stm32wl5_serial.c stm32wl5_start.c CHIP_CSRCS += stm32wl5_lse.c stm32wl5_idle.c -CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_flash.c stm32wl5_timerisr.c +CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_flash.c CHIP_CSRCS += stm32wl5_spi.c CSRCS-$(CONFIG_STM32_IPCC) = stm32wl5_ipcc.c diff --git a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c deleted file mode 100644 index 4de3d6b3936..00000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_timerisr.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include <stdint.h> -#include <time.h> - -#include <nuttx/debug.h> -#include <nuttx/arch.h> -#include <arch/board/board.h> - -#include "nvic.h" -#include "clock/clock.h" -#include "arm_internal.h" - -#include "chip.h" -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK) - * divided by 8. The SysTick can work either with this clock or with the - * Cortex clock (HCLK), configurable in the SysTick Control and Status - * register. - */ - -/* Power up default is HCLK, not HCLK/8. - * And I don't know now to re-configure it yet - */ - -#undef CONFIG_STM32_SYSTICK_HCLKd8 - -#ifdef CONFIG_STM32_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) -#else -# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) -#endif - -/* The size of the reload field is 24 bits. Verify that the reload value - * will fit in the reload register. - */ - -#if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -static int stm32_timerisr(int irq, uint32_t *regs, void *arg) -{ - /* Process timer interrupt */ - - nxsched_process_timer(); - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - uint32_t regval; - - /* Set the SysTick interrupt to the default priority */ - - regval = getreg32(NVIC_SYSH12_15_PRIORITY); - regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; - regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); - putreg32(regval, NVIC_SYSH12_15_PRIORITY); - - /* Make sure that the SYSTICK clock source is set correctly */ - -#if 0 /* Does not work. Comes up with HCLK source and I can't change it */ - regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32_SYSTICK_HCLKd8 - regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; -#else - regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; -#endif - putreg32(regval, NVIC_SYSTICK_CTRL); -#endif - - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); - - /* Attach the timer interrupt vector */ - - (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); - - /* Enable SysTick interrupts */ - - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | - NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); - - /* And enable the timer interrupt */ - - up_enable_irq(STM32_IRQ_SYSTICK); -}
