This is an automated email from the ASF dual-hosted git repository. anchao pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit ccade7a40035a3c0ba5f1b320cf49e4ad857dac0 Author: zhangyu117 <[email protected]> AuthorDate: Thu Jun 4 19:05:12 2026 +0800 arch/tricore: use tricore_mtcr replace __mtcr for tasking __mtcr is builtin func and will add isync for each __mtcr which is not necessary since we use UP_ISB Signed-off-by: zhangyu117 <[email protected]> --- arch/tricore/src/common/tricore_backtrace.c | 2 +- arch/tricore/src/common/tricore_csa.c | 8 ++++---- arch/tricore/src/common/tricore_doirq.c | 6 +++--- arch/tricore/src/common/tricore_registerdump.c | 4 ++-- arch/tricore/src/common/tricore_saveusercontext.c | 4 ++-- arch/tricore/src/common/tricore_svcall.c | 2 +- arch/tricore/src/common/tricore_trapcall.c | 15 ++++++++------- 7 files changed, 21 insertions(+), 20 deletions(-) diff --git a/arch/tricore/src/common/tricore_backtrace.c b/arch/tricore/src/common/tricore_backtrace.c index 5649af87ed9..4128d1787e8 100644 --- a/arch/tricore/src/common/tricore_backtrace.c +++ b/arch/tricore/src/common/tricore_backtrace.c @@ -127,7 +127,7 @@ int up_backtrace(struct tcb_s *tcb, if (tcb == NULL || tcb == rtcb) { - ret = backtrace(__mfcr(CPU_PCXI), buffer, size, &skip); + ret = backtrace(tricore_mfcr(CPU_PCXI), buffer, size, &skip); } else { diff --git a/arch/tricore/src/common/tricore_csa.c b/arch/tricore/src/common/tricore_csa.c index 239bd745a10..ff3d3c4b4a7 100644 --- a/arch/tricore/src/common/tricore_csa.c +++ b/arch/tricore/src/common/tricore_csa.c @@ -51,7 +51,7 @@ uintptr_t *tricore_alloc_csa(uintptr_t pc, uintptr_t sp, uintptr_t *plcsa; uintptr_t *pucsa; - plcsa = (uintptr_t *)tricore_csa2addr(__mfcr(CPU_FCX)); + plcsa = (uintptr_t *)tricore_csa2addr(tricore_mfcr(CPU_FCX)); /* DSYNC instruction should be executed immediately prior to the MTCR */ @@ -59,7 +59,7 @@ uintptr_t *tricore_alloc_csa(uintptr_t pc, uintptr_t sp, pucsa = (uintptr_t *)tricore_csa2addr(plcsa[REG_UPCXI]); - __mtcr(CPU_FCX, pucsa[REG_UPCXI]); + tricore_mtcr(CPU_FCX, pucsa[REG_UPCXI]); /* ISYNC instruction executed immediately following MTCR */ @@ -141,7 +141,7 @@ void tricore_reclaim_csa(uintptr_t pcxi) /* Look up the current free CSA head. */ - free = __mfcr(CPU_FCX); + free = tricore_mfcr(CPU_FCX); /* Join the current Free onto the Tail of what is being reclaimed. */ @@ -149,5 +149,5 @@ void tricore_reclaim_csa(uintptr_t pcxi) /* Move the head of the reclaimed into the Free. */ - __mtcr(CPU_FCX, head); + tricore_mtcr(CPU_FCX, head); } diff --git a/arch/tricore/src/common/tricore_doirq.c b/arch/tricore/src/common/tricore_doirq.c index c711702c6e8..d538aa070f9 100644 --- a/arch/tricore/src/common/tricore_doirq.c +++ b/arch/tricore/src/common/tricore_doirq.c @@ -56,8 +56,8 @@ IFX_INTERRUPT_INTERNAL(tricore_doirq, 0, 255) Ifx_CPU_ICR icr; uintptr_t *regs; - icr.U = __mfcr(CPU_ICR); - regs = tricore_csa2addr(__mfcr(CPU_PCXI)); + icr.U = tricore_mfcr(CPU_ICR); + regs = tricore_csa2addr(tricore_mfcr(CPU_PCXI)); if (*running_task != NULL) { @@ -106,7 +106,7 @@ IFX_INTERRUPT_INTERNAL(tricore_doirq, 0, 255) *running_task = tcb; - __mtcr(CPU_PCXI, tricore_addr2csa(tcb->xcp.regs)); + tricore_mtcr(CPU_PCXI, tricore_addr2csa(tcb->xcp.regs)); UP_ISB(); } diff --git a/arch/tricore/src/common/tricore_registerdump.c b/arch/tricore/src/common/tricore_registerdump.c index 44ff3aa8bdf..c4389340010 100644 --- a/arch/tricore/src/common/tricore_registerdump.c +++ b/arch/tricore/src/common/tricore_registerdump.c @@ -88,8 +88,8 @@ void tricore_dump_trapctrl(void) { _alert("PSTR:%-14.8" PRIX32 "DSTR:%-14.8" PRIX32 "DATR:%-14.8" PRIX32 "DEADD:%-13.8" PRIX32 "\n\n", - (uint32_t)__mfcr(CPU_PSTR), (uint32_t)__mfcr(CPU_DSTR), - (uint32_t)__mfcr(CPU_DATR), (uint32_t)__mfcr(CPU_DEADD)); + tricore_mfcr(CPU_PSTR), tricore_mfcr(CPU_DSTR), + tricore_mfcr(CPU_DATR), tricore_mfcr(CPU_DEADD)); } /**************************************************************************** diff --git a/arch/tricore/src/common/tricore_saveusercontext.c b/arch/tricore/src/common/tricore_saveusercontext.c index 25a46f82017..520b2568822 100644 --- a/arch/tricore/src/common/tricore_saveusercontext.c +++ b/arch/tricore/src/common/tricore_saveusercontext.c @@ -54,7 +54,7 @@ int up_saveusercontext(void *saveregs) uintptr_t pcxi; int csa_size = TC_CONTEXT_REGS * sizeof(uintptr_t); - pcxi = __mfcr(CPU_PCXI); + pcxi = tricore_mfcr(CPU_PCXI); regs = tricore_csa2addr(pcxi); memcpy((char *)saveregs + csa_size, regs, csa_size); @@ -62,7 +62,7 @@ int up_saveusercontext(void *saveregs) __asm("svlcx"); - regs = tricore_csa2addr(__mfcr(CPU_PCXI)); + regs = tricore_csa2addr(tricore_mfcr(CPU_PCXI)); memcpy(saveregs, regs, csa_size); /* lowcsa[REG_LPCXI] saves the upcsa's pcxi, but if lowcsa and upcsa is diff --git a/arch/tricore/src/common/tricore_svcall.c b/arch/tricore/src/common/tricore_svcall.c index 7177861fc99..5259ed7fd1e 100644 --- a/arch/tricore/src/common/tricore_svcall.c +++ b/arch/tricore/src/common/tricore_svcall.c @@ -62,7 +62,7 @@ void tricore_svcall(volatile void *trap) uintptr_t *regs; uint32_t cmd; - regs = (uintptr_t *)__mfcr(CPU_PCXI); + regs = (uintptr_t *)tricore_mfcr(CPU_PCXI); /* DSYNC instruction should be executed immediately prior to the MTCR */ diff --git a/arch/tricore/src/common/tricore_trapcall.c b/arch/tricore/src/common/tricore_trapcall.c index 673819e2bf1..5dbb91c4c3e 100644 --- a/arch/tricore/src/common/tricore_trapcall.c +++ b/arch/tricore/src/common/tricore_trapcall.c @@ -186,9 +186,9 @@ int tricore_insterrorstrap(uint32_t tid, void *context, void *arg) _alert("\tCoprocessor Trap Synchronous Error\n"); # ifdef CONFIG_ARCH_HAVE_FPU _alert("\tFPU_SYNC_TRAP:%" PRIX32 "\n\n", - (uint32_t)__mfcr(FPU_SYNC_TRAP_REG)); - __mtcr(FPU_SYNC_TRAP_REG, - __mfcr(FPU_SYNC_TRAP_REG) | (1U << FPU_TRAP_TCL_SHIFT)); + tricore_mfcr(FPU_SYNC_TRAP_REG)); + tricore_mtcr(FPU_SYNC_TRAP_REG, tricore_mfcr(FPU_SYNC_TRAP_REG) | + (1U << FPU_TRAP_TCL_SHIFT)); # endif } #endif @@ -272,9 +272,10 @@ int tricore_bustrap(uint32_t tid, void *context, void *arg) _alert("\tCoprocessor Trap Asynchronous Error\n"); #ifdef CONFIG_ARCH_HAVE_FPU _alert("\tFPU_ASYNC_TRAP:%" PRIX32 "\n\n", - (uint32_t)__mfcr(FPU_ASYNC_TRAP_REG)); - __mtcr(FPU_ASYNC_TRAP_REG, - __mfcr(FPU_ASYNC_TRAP_REG) | (1U << FPU_TRAP_TCL_SHIFT)); + tricore_mfcr(FPU_ASYNC_TRAP_REG)); + tricore_mtcr(FPU_ASYNC_TRAP_REG, tricore_mfcr(FPU_ASYNC_TRAP_REG) | + (1U << FPU_TRAP_TCL_SHIFT)); + UP_ISB(); #endif } @@ -340,7 +341,7 @@ void tricore_trapcall(volatile void *trap) tricore_trapinfo(trap); - regs = tricore_csa2addr(__mfcr(CPU_PCXI)); + regs = tricore_csa2addr(tricore_mfcr(CPU_PCXI)); pcxi = regs[REG_UPCXI]; regs = tricore_csa2addr(pcxi);
