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commit 53e53af649ee78efe0fb977a49d83d2be95391a8 Author: raiden00pl <[email protected]> AuthorDate: Sun Oct 11 11:30:23 2026 +0200 arch/arm: enable LPTIM on all STM32 families The common LPTIM driver works on every STM32 with an LPTIM, so select the LPTIM instances available on each chip. The instances are taken from the reference SVD files and checked against the ST CMSIS device headers (the STM32G070 SVD file lists LPTIM1/2, but the device has no LPTIM): - STM32C5: LPTIM1 - STM32F410: LPTIM1 - STM32G0: LPTIM1-2, except G030, G050, G070 and G0B0 - STM32H5: LPTIM1-2, LPTIM3-6 on H56x/H57x only - STM32H7: LPTIM1-5, LPTIM1-3 on H7A3/H7B0/H7B3 - STM32L0: LPTIM1 - STM32L5: LPTIM1-3 - STM32N6: LPTIM1-5 - STM32U3: LPTIM1-4 - STM32U5: LPTIM2 added - STM32WB: LPTIM2 added - STM32WL5: LPTIM1-3 STM32_LPTIM2 and STM32_LPTIM5 depend on the STM32_HAVE_LPTIMn flags instead of chip lists and STM32_LPTIM6 is added. The missing STM32F410 LPTIM1 base address, interrupt and RCC bits and the STM32N6 RCC APB4L registers and LPTIM bits are added. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- Documentation/guides/chip-specific/stm32_ports.rst | 24 +++++++++++++++------- arch/arm/include/stm32f4/irq.h | 2 +- arch/arm/src/common/stm32/Kconfig.have | 6 ++++++ arch/arm/src/common/stm32/Kconfig.periph | 9 ++++++-- arch/arm/src/stm32c5/Kconfig | 1 + arch/arm/src/stm32f4/Kconfig | 1 + arch/arm/src/stm32f4/hardware/stm32_rcc.h | 2 ++ .../src/stm32f4/hardware/stm32f40xxx_memorymap.h | 1 + arch/arm/src/stm32g0/Kconfig | 16 +++++++++++++++ arch/arm/src/stm32h5/Kconfig | 7 ++++--- arch/arm/src/stm32h7/Kconfig | 4 +++- arch/arm/src/stm32l0/Kconfig | 1 + arch/arm/src/stm32l5/Kconfig | 3 +++ arch/arm/src/stm32n6/Kconfig | 5 +++++ arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h | 20 ++++++++++++++++++ arch/arm/src/stm32u3/Kconfig | 4 ++++ arch/arm/src/stm32u5/Kconfig | 1 + arch/arm/src/stm32wb/Kconfig | 1 + arch/arm/src/stm32wl5/Kconfig | 3 +++ 19 files changed, 97 insertions(+), 14 deletions(-) diff --git a/Documentation/guides/chip-specific/stm32_ports.rst b/Documentation/guides/chip-specific/stm32_ports.rst index 1c07c7475ac..21f88a369d1 100644 --- a/Documentation/guides/chip-specific/stm32_ports.rst +++ b/Documentation/guides/chip-specific/stm32_ports.rst @@ -293,7 +293,7 @@ I3C to be done not supported ICACHE to be done not supported IWDG v3 arch/arm/src/common/stm32/stm32_iwdg.c LPDMA GPDMA arch/arm/src/common/stm32/stm32_dma_gpdma.c -LPTIM to be done not supported +LPTIM v2 arch/arm/src/common/stm32/stm32_lptim.c LPUART M33 v3 arch/arm/src/common/stm32/stm32_serial_m33_v3.c PWR to be done not supported RAMCFG to be done not supported @@ -447,6 +447,7 @@ GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c HASH to be done not supported I2C v1 arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c IWDG v1 arch/arm/src/common/stm32/stm32_iwdg.c +LPTIM v1 arch/arm/src/common/stm32/stm32_lptim.c LTDC v1 arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c QUADSPI to be done not supported RCC to be done arch/arm/src/stm32f4/stm32_rcc.c @@ -480,6 +481,7 @@ GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c HRTIM v1 arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c I2C v2 arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c IWDG v2 arch/arm/src/common/stm32/stm32_iwdg.c +LPTIM v1 arch/arm/src/common/stm32/stm32_lptim.c OPAMP v1 arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c RCC to be done arch/arm/src/stm32g4/stm32_rcc.c RNG v1 arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c @@ -545,6 +547,7 @@ FMC/FSMC to be done arch/arm/src/stm32f7/stm32_fmc.c GPIO to be done arch/arm/src/stm32f7/stm32_gpio.c I2C to be done arch/arm/src/stm32f7/stm32_i2c.c IWDG v1 arch/arm/src/common/stm32/stm32_iwdg.c +LPTIM v1 arch/arm/src/common/stm32/stm32_lptim.c LTDC to be done arch/arm/src/stm32f7/stm32_ltdc.c PWR to be done arch/arm/src/stm32f7/stm32_pwr.c QUADSPI to be done arch/arm/src/stm32f7/stm32_qspi.c @@ -584,6 +587,7 @@ FLASH G0/C0 not supported GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m0_v1.c I2C v1 arch/arm/src/common/stm32/stm32_i2c_m0_v1.c IWDG v2 arch/arm/src/common/stm32/stm32_iwdg.c +LPTIM v1 arch/arm/src/common/stm32/stm32_lptim.c PWR G0 not supported RCC to be done arch/arm/src/stm32g0/stm32_rcc.c RNG v1 arch/arm/src/common/stm32/stm32_rng_m0_v1.c @@ -688,6 +692,7 @@ FLASH M0 v1 not supported GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m0_v1.c I2C v1 arch/arm/src/common/stm32/stm32_i2c_m0_v1.c IWDG v1 arch/arm/src/common/stm32/stm32_iwdg.c +LPTIM v1 arch/arm/src/common/stm32/stm32_lptim.c PWR v1 arch/arm/src/common/stm32/stm32_pwr_m0_v1.c RCC to be done arch/arm/src/stm32l0/stm32_rcc.c RNG v1 arch/arm/src/common/stm32/stm32_rng_m0_v1.c @@ -744,6 +749,7 @@ GTZC to be done not supported HASH to be done not supported I2C to be done not supported IWDG v2 arch/arm/src/common/stm32/stm32_iwdg.c +LPTIM v1 arch/arm/src/common/stm32/stm32_lptim.c OCTOSPI to be done not supported PWR to be done arch/arm/src/stm32l5/stm32l5_pwr.c RCC to be done arch/arm/src/stm32l5/stm32l5_rcc.c @@ -751,7 +757,7 @@ RNG to be done not supported RTC to be done not supported SDMMC to be done not supported SPI/I2S to be done arch/arm/src/stm32l5/stm32l5_spi.c -TIM/LPTIM v2 arch/arm/src/common/stm32/stm32_tim.c +TIM v2 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/stm32l5/stm32l5_serial.c USB device not supported WWDG v2 arch/arm/src/common/stm32/stm32_wwdg.c @@ -772,6 +778,7 @@ GPIO to be done arch/arm/src/stm32n6/stm32_gpio.c GPDMA to be done not supported I2C to be done not supported IWDG v3 arch/arm/src/common/stm32/stm32_iwdg.c +LPTIM v2 arch/arm/src/common/stm32/stm32_lptim.c PWR to be done arch/arm/src/stm32n6/stm32_pwr.c RCC to be done arch/arm/src/stm32n6/stm32_rcc.c SPI/I2S to be done not supported @@ -800,7 +807,7 @@ GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m0_v1.c I2C v1 arch/arm/src/common/stm32/stm32_i2c_m0_v1.c IWDG v3 arch/arm/src/common/stm32/stm32_iwdg.c LCD to be done not supported -LPTIM to be done not supported +LPTIM v2 arch/arm/src/common/stm32/stm32_lptim.c PWR G0 arch/arm/src/common/stm32/stm32_pwr_m0_g0.c RCC to be done arch/arm/src/stm32u0/stm32_rcc.c RNG v1 arch/arm/src/common/stm32/stm32_rng_m0_v1.c @@ -841,8 +848,8 @@ HSP to be done not supported I2C to be done not supported I3C to be done not supported ICACHE to be done not supported -LPTIM to be done not supported IWDG v3 arch/arm/src/common/stm32/stm32_iwdg.c +LPTIM v2 arch/arm/src/common/stm32/stm32_lptim.c LPUART M33 v3 arch/arm/src/common/stm32/stm32_serial_m33_v3.c OCTOSPI to be done not supported OPAMP to be done not supported @@ -882,6 +889,7 @@ GPDMA GPDMA arch/arm/src/common/stm32/stm32_dma_gpdma.c HASH to be done not supported I2C to be done arch/arm/src/stm32u5/stm32_i2c.c ICACHE to be done not supported +LPTIM v2 arch/arm/src/common/stm32/stm32_lptim.c OCTOSPI to be done not supported PWR to be done arch/arm/src/stm32u5/stm32_pwr.c RCC to be done arch/arm/src/stm32u5/stm32_rcc.c @@ -891,7 +899,7 @@ SAES/AES to be done not supported SDMMC to be done not supported SPI/I2S to be done arch/arm/src/stm32u5/stm32_spi.c TAMP to be done not supported -TIM/LPTIM v3 arch/arm/src/common/stm32/stm32_tim.c +TIM v3 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/stm32u5/stm32_serial.c USB device not supported ============ ============ =========================================== @@ -912,13 +920,14 @@ GPIO to be done arch/arm/src/stm32wb/stm32wb_gpio.c I2C to be done arch/arm/src/stm32wb/stm32wb_i2c.c IPCC to be done arch/arm/src/stm32wb/stm32wb_ipcc.c IWDG v2 arch/arm/src/common/stm32/stm32_iwdg.c +LPTIM v1 arch/arm/src/common/stm32/stm32_lptim.c PWR to be done arch/arm/src/stm32wb/stm32wb_pwr.c Radio to be done not supported RCC to be done arch/arm/src/stm32wb/stm32wb_rcc.c RNG to be done not supported RTC to be done arch/arm/src/stm32wb/stm32wb_rtc.c SPI/I2S to be done arch/arm/src/stm32wb/stm32wb_spi.c -TIM/LPTIM v2 arch/arm/src/common/stm32/stm32_tim.c +TIM v2 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v4 arch/arm/src/stm32wb/stm32wb_serial.c USB device not supported WWDG v2 arch/arm/src/common/stm32/stm32_wwdg.c @@ -940,13 +949,14 @@ GPIO to be done arch/arm/src/stm32wl5/stm32wl5_gpio.c I2C to be done not supported IPCC to be done arch/arm/src/stm32wl5/stm32wl5_ipcc.c IWDG v2 arch/arm/src/common/stm32/stm32_iwdg.c +LPTIM v1 arch/arm/src/common/stm32/stm32_lptim.c PWR to be done arch/arm/src/stm32wl5/stm32wl5_pwr.c Radio to be done not supported RCC to be done arch/arm/src/stm32wl5/stm32wl5_rcc.c RNG to be done not supported RTC to be done not supported SPI/I2S to be done arch/arm/src/stm32wl5/stm32wl5_spi.c -TIM/LPTIM v2 arch/arm/src/common/stm32/stm32_tim.c +TIM v2 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v3 arch/arm/src/stm32wl5/stm32wl5_serial.c USB to be done not supported WWDG v2 arch/arm/src/common/stm32/stm32_wwdg.c diff --git a/arch/arm/include/stm32f4/irq.h b/arch/arm/include/stm32f4/irq.h index eb9eb5e3438..198f1b489d2 100644 --- a/arch/arm/include/stm32f4/irq.h +++ b/arch/arm/include/stm32f4/irq.h @@ -323,7 +323,7 @@ # define STM32_IRQ_RESERVED94 (STM32_IRQ_FIRST+94) /* 94: Reserved */ # define STM32_IRQ_RESERVED95 (STM32_IRQ_FIRST+95) /* 95: Reserved */ # define STM32_IRQ_RESERVED96 (STM32_IRQ_FIRST+96) /* 96: Reserved */ -# define STM32_IRQ_RESERVED97 (STM32_IRQ_FIRST+97) /* 97: Reserved */ +# define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST+97) /* 97: LPTIM1 global interrupt */ #endif #if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \ diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index ba432fccb42..930651fc55d 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -1065,6 +1065,12 @@ config STM32_HAVE_LPTIM3 config STM32_HAVE_LPTIM4 bool +config STM32_HAVE_LPTIM5 + bool + +config STM32_HAVE_LPTIM6 + bool + # TSC capabilities config STM32_HAVE_TSC diff --git a/arch/arm/src/common/stm32/Kconfig.periph b/arch/arm/src/common/stm32/Kconfig.periph index c23bf08fa95..df373bdb9ac 100644 --- a/arch/arm/src/common/stm32/Kconfig.periph +++ b/arch/arm/src/common/stm32/Kconfig.periph @@ -837,7 +837,7 @@ config STM32_TIM17 config STM32_LPTIM2 bool "LPTIM2" - depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 + depends on STM32_HAVE_LPTIM2 select STM32_LPTIM config STM32_LPTIM3 @@ -852,7 +852,12 @@ config STM32_LPTIM4 config STM32_LPTIM5 bool "LPTIM5" - depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32H5 + depends on STM32_HAVE_LPTIM5 + select STM32_LPTIM + +config STM32_LPTIM6 + bool "LPTIM6" + depends on STM32_HAVE_LPTIM6 select STM32_LPTIM config STM32_HRTIM1 diff --git a/arch/arm/src/stm32c5/Kconfig b/arch/arm/src/stm32c5/Kconfig index 8695ba37ca2..8153b37f9bf 100644 --- a/arch/arm/src/stm32c5/Kconfig +++ b/arch/arm/src/stm32c5/Kconfig @@ -20,6 +20,7 @@ config STM32_C5_PERIPHERALS select STM32_HAVE_IP_DBGMCU_V5 select STM32_HAVE_IP_LPTIM_V2 select STM32_HAVE_IP_WDG_V3 + select STM32_HAVE_LPTIM1 select STM32_HAVE_IP_USART_M33_V3 select STM32_HAVE_LPUART1 select STM32_HAVE_UART4 diff --git a/arch/arm/src/stm32f4/Kconfig b/arch/arm/src/stm32f4/Kconfig index 4b06a3123c8..2ca9d7b6d40 100644 --- a/arch/arm/src/stm32f4/Kconfig +++ b/arch/arm/src/stm32f4/Kconfig @@ -334,6 +334,7 @@ config STM32_STM32F401 config STM32_STM32F410 bool default n + select STM32_HAVE_LPTIM1 select STM32_HAVE_USART6 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 diff --git a/arch/arm/src/stm32f4/hardware/stm32_rcc.h b/arch/arm/src/stm32f4/hardware/stm32_rcc.h index 1fd8fa4670f..3b449105061 100644 --- a/arch/arm/src/stm32f4/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32f4/hardware/stm32_rcc.h @@ -327,6 +327,7 @@ #define RCC_APB1RSTR_TIM12RST (1 << 6) /* Bit 6: TIM12 reset */ #define RCC_APB1RSTR_TIM13RST (1 << 7) /* Bit 7: TIM13 reset */ #define RCC_APB1RSTR_TIM14RST (1 << 8) /* Bit 8: TIM14 reset */ +#define RCC_APB1RSTR_LPTIM1RST (1 << 9) /* Bit 9: LPTIM1 reset */ #define RCC_APB1RSTR_WWDGRST (1 << 11) /* Bit 11: Window watchdog reset */ #define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */ #define RCC_APB1RSTR_SPI3RST (1 << 15) /* Bit 15: SPI 3 reset */ @@ -469,6 +470,7 @@ #define RCC_APB1ENR_TIM12EN (1 << 6) /* Bit 6: TIM12 clock enable */ #define RCC_APB1ENR_TIM13EN (1 << 7) /* Bit 7: TIM13 clock enable */ #define RCC_APB1ENR_TIM14EN (1 << 8) /* Bit 8: TIM14 clock enable */ +#define RCC_APB1ENR_LPTIM1EN (1 << 9) /* Bit 9: LPTIM1 clock enable */ #define RCC_APB1ENR_RTCAPBEN (1 << 10) /* Bit 10: RTCAPB clock enable */ #define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window watchdog clock enable */ #define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI2 clock enable */ diff --git a/arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h index c1549f7b994..1e1acbc8392 100644 --- a/arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h @@ -133,6 +133,7 @@ #define STM32_TIM12_BASE 0x40001800 /* 0x40001800-0x40001bff: TIM12 timer */ #define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff: TIM13 timer */ #define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 timer */ +#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 timer */ #define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP registers */ #define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: Window watchdog (WWDG) */ #define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: Independent watchdog (IWDG) */ diff --git a/arch/arm/src/stm32g0/Kconfig b/arch/arm/src/stm32g0/Kconfig index e2cb2645946..337c5f3968d 100644 --- a/arch/arm/src/stm32g0/Kconfig +++ b/arch/arm/src/stm32g0/Kconfig @@ -261,6 +261,8 @@ config STM32_STM32G031 bool default n select STM32_STM32G0 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 select STM32_HAVE_TIM2 select STM32_STM32G03X select STM32_HAVE_LPUART1 @@ -273,6 +275,8 @@ config STM32_STM32G041 bool default n select STM32_STM32G0 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 select STM32_HAVE_TIM2 select STM32_HAVE_RNG select STM32_HAVE_AES @@ -288,6 +292,8 @@ config STM32_STM32G051 bool default n select STM32_STM32G0 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 select STM32_HAVE_TIM2 select STM32_STM32G05X select STM32_HAVE_DAC1 @@ -306,6 +312,8 @@ config STM32_STM32G061 bool default n select STM32_STM32G0 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 select STM32_HAVE_TIM2 select STM32_HAVE_RNG select STM32_HAVE_AES @@ -327,6 +335,8 @@ config STM32_STM32G071 bool default n select STM32_STM32G0 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 select STM32_HAVE_TIM2 select STM32_STM32G07X select STM32_HAVE_DAC1 @@ -350,6 +360,8 @@ config STM32_STM32G081 bool default n select STM32_STM32G0 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 select STM32_HAVE_TIM2 select STM32_HAVE_USART3 select STM32_HAVE_USART4 @@ -376,6 +388,8 @@ config STM32_STM32G0B1 bool default n select STM32_STM32G0 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 select STM32_HAVE_TIM2 select STM32_STM32G0BX select STM32_HAVE_SPI2 @@ -414,6 +428,8 @@ config STM32_STM32G0C1 bool default n select STM32_STM32G0 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 select STM32_HAVE_DMA2 select STM32_HAVE_USART3 select STM32_HAVE_USART4 diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index 090f87e0a50..9542444d7f8 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -23,9 +23,6 @@ config STM32_H5_PERIPHERALS select STM32_HAVE_I2C2 select STM32_HAVE_LPTIM1 select STM32_HAVE_LPTIM2 - select STM32_HAVE_LPTIM3 - select STM32_HAVE_LPTIM4 - select STM32_HAVE_LPTIM5 select STM32_HAVE_RNG select STM32_HAVE_SPI1 select STM32_HAVE_SPI2 @@ -164,6 +161,10 @@ config STM32_H56_H57_PERIPHERALS select STM32_HAVE_FDCAN1 select STM32_HAVE_FDCAN2 select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_LPTIM3 + select STM32_HAVE_LPTIM4 + select STM32_HAVE_LPTIM5 + select STM32_HAVE_LPTIM6 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 select STM32_HAVE_TIM2_32BITS diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index c396e1da7e4..c10de41190a 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -58,8 +58,10 @@ config STM32_H7_PERIPHERALS select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 select STM32_HAVE_LPTIM3 - select STM32_HAVE_LPTIM4 + select STM32_HAVE_LPTIM4 if !STM32_STM32H7B3XX + select STM32_HAVE_LPTIM5 if !STM32_STM32H7B3XX select STM32_HAVE_OTGFS select STM32_HAVE_RTC_SUBSECONDS select STM32_HAVE_RTC_MAGIC diff --git a/arch/arm/src/stm32l0/Kconfig b/arch/arm/src/stm32l0/Kconfig index b15708f6064..32715d24b33 100644 --- a/arch/arm/src/stm32l0/Kconfig +++ b/arch/arm/src/stm32l0/Kconfig @@ -220,6 +220,7 @@ config STM32_STM32L0 select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 select STM32_HAVE_IP_DBGMCU_V3 select STM32_HAVE_IP_LPTIM_V1 + select STM32_HAVE_LPTIM1 select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_DMA_V1_7CH select STM32_HAVE_IP_EXTI_V1 diff --git a/arch/arm/src/stm32l5/Kconfig b/arch/arm/src/stm32l5/Kconfig index aaddb0aa458..7ca81ed8666 100644 --- a/arch/arm/src/stm32l5/Kconfig +++ b/arch/arm/src/stm32l5/Kconfig @@ -16,6 +16,9 @@ config STM32_L5_PERIPHERALS select STM32_HAVE_IP_DBGMCU_V4 select STM32_HAVE_IP_LPTIM_V1 select STM32_HAVE_IP_WDG_V2 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_LPTIM3 select STM32_HAVE_IP_USART_M33_V3 select STM32_HAVE_RTC_SUBSECONDS select STM32_HAVE_RTC_MAGIC diff --git a/arch/arm/src/stm32n6/Kconfig b/arch/arm/src/stm32n6/Kconfig index a40d82f5de8..97dd4b79cf1 100644 --- a/arch/arm/src/stm32n6/Kconfig +++ b/arch/arm/src/stm32n6/Kconfig @@ -14,6 +14,11 @@ config STM32_N6_PERIPHERALS select STM32_HAVE_IP_DBGMCU_V8 select STM32_HAVE_IP_LPTIM_V2 select STM32_HAVE_IP_WDG_V3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_LPTIM3 + select STM32_HAVE_LPTIM4 + select STM32_HAVE_LPTIM5 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 diff --git a/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h b/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h index 55820af77aa..4f3ebaa0f5f 100644 --- a/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h +++ b/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h @@ -50,6 +50,7 @@ #define STM32_RCC_CCIPR13_OFFSET 0x0174 /* Peripheral kernel clock select register 13 */ #define STM32_RCC_APB1LRSTR_OFFSET 0x0224 /* APB1 peripheral reset register 1 */ #define STM32_RCC_APB2RSTR_OFFSET 0x022c /* APB2 peripheral reset register */ +#define STM32_RCC_APB4LRSTR_OFFSET 0x0234 /* APB4 peripheral reset register 1 */ /* Peripheral clock enable / set / clear register offsets. Each enable * register (xxxENR) has a paired set register (xxxENSR) that performs an @@ -62,6 +63,7 @@ #define STM32_RCC_AHB4ENR_OFFSET 0x025c /* AHB4 peripheral clock enable register */ #define STM32_RCC_APB1LENR_OFFSET 0x0264 /* APB1 peripheral clock enable register 1 */ #define STM32_RCC_APB2ENR_OFFSET 0x026c /* APB2 peripheral clock enable register */ +#define STM32_RCC_APB4LENR_OFFSET 0x0274 /* APB4 peripheral clock enable register 1 */ #define STM32_RCC_APB4HENR_OFFSET 0x0278 /* APB4 peripheral clock enable register 2 */ #define STM32_RCC_BUSLPENR_OFFSET 0x0284 /* Bus clocks enable in Sleep mode */ #define STM32_RCC_MEMLPENR_OFFSET 0x028c /* SRAM clocks enable in Sleep mode */ @@ -102,6 +104,7 @@ #define STM32_RCC_CCIPR13 (STM32_RCC_BASE + STM32_RCC_CCIPR13_OFFSET) #define STM32_RCC_APB1LRSTR (STM32_RCC_BASE + STM32_RCC_APB1LRSTR_OFFSET) #define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB4LRSTR (STM32_RCC_BASE + STM32_RCC_APB4LRSTR_OFFSET) #define STM32_RCC_DIVENR (STM32_RCC_BASE + STM32_RCC_DIVENR_OFFSET) #define STM32_RCC_DIVENSR (STM32_RCC_BASE + STM32_RCC_DIVENSR_OFFSET) @@ -110,6 +113,7 @@ #define STM32_RCC_AHB4ENR (STM32_RCC_BASE + STM32_RCC_AHB4ENR_OFFSET) #define STM32_RCC_APB1LENR (STM32_RCC_BASE + STM32_RCC_APB1LENR_OFFSET) #define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_APB4LENR (STM32_RCC_BASE + STM32_RCC_APB4LENR_OFFSET) #define STM32_RCC_APB4HENR (STM32_RCC_BASE + STM32_RCC_APB4HENR_OFFSET) #define STM32_RCC_BUSLPENR (STM32_RCC_BASE + STM32_RCC_BUSLPENR_OFFSET) #define STM32_RCC_MEMLPENR (STM32_RCC_BASE + STM32_RCC_MEMLPENR_OFFSET) @@ -250,6 +254,7 @@ #define RCC_APB1LENR_TIM11EN (1 << 13) /* Bit 13: TIM11 enable */ #define RCC_APB1LENR_TIM10EN (1 << 12) /* Bit 12: TIM10 enable */ #define RCC_APB1LENR_WWDGEN (1 << 11) /* Bit 11: WWDG enable */ +#define RCC_APB1LENR_LPTIM1EN (1 << 9) /* Bit 9: LPTIM1 enable */ #define RCC_APB1LENR_TIM14EN (1 << 8) /* Bit 8: TIM14 enable */ #define RCC_APB1LENR_TIM13EN (1 << 7) /* Bit 7: TIM13 enable */ #define RCC_APB1LENR_TIM12EN (1 << 6) /* Bit 6: TIM12 enable */ @@ -276,6 +281,7 @@ #define RCC_APB1LRSTR_TIM11RST (1 << 13) /* Bit 13: TIM11 reset */ #define RCC_APB1LRSTR_TIM10RST (1 << 12) /* Bit 12: TIM10 reset */ #define RCC_APB1LRSTR_WWDGRST (1 << 11) /* Bit 11: WWDG reset */ +#define RCC_APB1LRSTR_LPTIM1RST (1 << 9) /* Bit 9: LPTIM1 reset */ #define RCC_APB1LRSTR_TIM14RST (1 << 8) /* Bit 8: TIM14 reset */ #define RCC_APB1LRSTR_TIM13RST (1 << 7) /* Bit 7: TIM13 reset */ #define RCC_APB1LRSTR_TIM12RST (1 << 6) /* Bit 6: TIM12 reset */ @@ -296,6 +302,20 @@ #define RCC_APB2RSTR_TIM8RST (1 << 1) /* Bit 1: TIM8 reset */ #define RCC_APB2RSTR_TIM1RST (1 << 0) /* Bit 0: TIM1 reset */ +/* APB4 peripheral clock enable register 1 */ + +#define RCC_APB4LENR_LPTIM5EN (1 << 12) /* Bit 12: LPTIM5 enable */ +#define RCC_APB4LENR_LPTIM4EN (1 << 11) /* Bit 11: LPTIM4 enable */ +#define RCC_APB4LENR_LPTIM3EN (1 << 10) /* Bit 10: LPTIM3 enable */ +#define RCC_APB4LENR_LPTIM2EN (1 << 9) /* Bit 9: LPTIM2 enable */ + +/* APB4 peripheral reset register 1 */ + +#define RCC_APB4LRSTR_LPTIM5RST (1 << 12) /* Bit 12: LPTIM5 reset */ +#define RCC_APB4LRSTR_LPTIM4RST (1 << 11) /* Bit 11: LPTIM4 reset */ +#define RCC_APB4LRSTR_LPTIM3RST (1 << 10) /* Bit 10: LPTIM3 reset */ +#define RCC_APB4LRSTR_LPTIM2RST (1 << 9) /* Bit 9: LPTIM2 reset */ + /* APB4 peripheral clock enable register 2 */ #define RCC_APB4HENR_BSECEN (1 << 1) /* Bit 1: BSEC enable */ diff --git a/arch/arm/src/stm32u3/Kconfig b/arch/arm/src/stm32u3/Kconfig index 363a4ba27e8..71e96c21105 100644 --- a/arch/arm/src/stm32u3/Kconfig +++ b/arch/arm/src/stm32u3/Kconfig @@ -18,6 +18,10 @@ config STM32_U3_PERIPHERALS select STM32_HAVE_IP_DBGMCU_V5 select STM32_HAVE_IP_LPTIM_V2 select STM32_HAVE_IP_WDG_V3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_LPTIM3 + select STM32_HAVE_LPTIM4 select STM32_HAVE_IP_USART_M33_V3 select STM32_HAVE_SYSCFG select STM32_HAVE_USART1 diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index 2246104e95b..fabd4af7828 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -30,6 +30,7 @@ config STM32_U5_PERIPHERALS select STM32_HAVE_I2C3 select STM32_HAVE_I2C4 select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 select STM32_HAVE_LPTIM3 select STM32_HAVE_LPTIM4 select STM32_HAVE_LPUART1 diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index 64b42934130..70710c3ecb1 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -18,6 +18,7 @@ config STM32_WB_PERIPHERALS select STM32_HAVE_SRAM2B select STM32_HAVE_I2C1 select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 select STM32_HAVE_LPUART1 if STM32_HAVE_LPUART select STM32_HAVE_RTC_SUBSECONDS select STM32_HAVE_RTC_MAGIC diff --git a/arch/arm/src/stm32wl5/Kconfig b/arch/arm/src/stm32wl5/Kconfig index baacf43cdf2..4d2bc0218ca 100644 --- a/arch/arm/src/stm32wl5/Kconfig +++ b/arch/arm/src/stm32wl5/Kconfig @@ -44,6 +44,9 @@ config STM32_STM32WL5XXX select STM32_HAVE_IP_DBGMCU_V6 select STM32_HAVE_IP_LPTIM_V1 select STM32_HAVE_IP_WDG_V2 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_LPTIM3 config STM32_STM32WL5XXX_CPU1 bool
