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commit 2e893d2a5ad6666bea06d7a9f21beb6be23d885a Author: raiden00pl <[email protected]> AuthorDate: Mon Oct 26 13:21:35 2026 +0100 arch/arm/src/common/stm32: move STM32H5 LPTIM driver to common code Move the STM32H5 LPTIM driver and its register header to common/stm32 and use it on STM32H7 instead of the local copy. The RCC clock enable and reset bits of each instance come from stm32_lptim_clk.h, detected from the family RCC definitions like stm32_tim_clk.h does for TIM. The ARR and CMP write wait of the STM32H5 driver is kept for STM32_HAVE_IP_LPTIM_V2 only, the STM32H7 driver had none. deinit() clears the RCC clock enable bit, the STM32H7 driver cleared the bit in the sleep mode clock enable register. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- .github/CODEOWNERS | 6 +- arch/arm/src/common/stm32/CMakeLists.txt | 5 + arch/arm/src/common/stm32/Kconfig.have | 8 + arch/arm/src/common/stm32/Make.defs | 5 + .../stm32}/hardware/stm32_lptim.h | 8 +- .../src/{stm32h5 => common/stm32}/stm32_lptim.c | 68 ++- .../src/{stm32h7 => common/stm32}/stm32_lptim.h | 8 +- arch/arm/src/common/stm32/stm32_lptim_clk.h | 163 +++++++ arch/arm/src/stm32h5/CMakeLists.txt | 4 - arch/arm/src/stm32h5/Kconfig | 1 + arch/arm/src/stm32h5/Make.defs | 4 - arch/arm/src/stm32h5/stm32_lptim.h | 106 ----- arch/arm/src/stm32h7/CMakeLists.txt | 4 - arch/arm/src/stm32h7/Kconfig | 2 + arch/arm/src/stm32h7/Make.defs | 4 - arch/arm/src/stm32h7/hardware/stm32_lptim.h | 178 -------- arch/arm/src/stm32h7/stm32_lptim.c | 471 --------------------- 17 files changed, 241 insertions(+), 804 deletions(-) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index bf2d0aa1033..ef44e9566ec 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -1637,6 +1637,7 @@ arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h [email protected] david_s arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/hardware/stm32_lcd.h [email protected] [email protected] [email protected] +arch/arm/src/common/stm32/hardware/stm32_lptim.h [email protected] [email protected] [email protected] arch/arm/src/common/stm32/hardware/stm32_ltdc.h [email protected] [email protected] [email protected] arch/arm/src/common/stm32/hardware/stm32_otghs.h [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/hardware/stm32_pwr.h [email protected] [email protected] [email protected] [email protected] @@ -1787,6 +1788,8 @@ arch/arm/src/common/stm32/stm32_lowputc.h [email protected] [email protected] arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c [email protected] [email protected] [email protected] [email protected] [email protected] +arch/arm/src/common/stm32/stm32_lptim.c [email protected] [email protected] [email protected] +arch/arm/src/common/stm32/stm32_lptim.h [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_lse_m0_v1.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/common/stm32/stm32_lsi.c [email protected] [email protected] [email protected] [email protected] @@ -4150,7 +4153,6 @@ arch/arm/src/stm32h7/hardware/stm32_fmc.h [email protected] [email protected] arch/arm/src/stm32h7/hardware/stm32_gpio.h [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32h7/hardware/stm32_hsem.h [email protected] [email protected] arch/arm/src/stm32h7/hardware/stm32_i2c.h [email protected] [email protected] [email protected] [email protected] -arch/arm/src/stm32h7/hardware/stm32_lptim.h [email protected] [email protected] [email protected] arch/arm/src/stm32h7/hardware/stm32_ltdc.h [email protected] [email protected] arch/arm/src/stm32h7/hardware/stm32_mdma.h [email protected] [email protected] [email protected] arch/arm/src/stm32h7/hardware/stm32_memorymap.h [email protected] [email protected] [email protected] [email protected] @@ -4216,8 +4218,6 @@ arch/arm/src/stm32h7/stm32_i2c.h [email protected] [email protected] pet arch/arm/src/stm32h7/stm32_irq.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32h7/stm32_lowputc.c [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32h7/stm32_lowputc.h [email protected] [email protected] -arch/arm/src/stm32h7/stm32_lptim.c [email protected] [email protected] [email protected] -arch/arm/src/stm32h7/stm32_lptim.h [email protected] [email protected] [email protected] arch/arm/src/stm32h7/stm32_lse.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32h7/stm32_ltdc.c [email protected] [email protected] [email protected] [email protected] [email protected] arch/arm/src/stm32h7/stm32_ltdc.h [email protected] [email protected] [email protected] diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 161cc0ac3da..a725940137f 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -97,6 +97,11 @@ if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c) endif() +if(CONFIG_STM32_LPTIM AND (CONFIG_STM32_HAVE_IP_LPTIM_V1 OR + CONFIG_STM32_HAVE_IP_LPTIM_V2)) + list(APPEND SRCS stm32_lptim.c) +endif() + if(CONFIG_STM32_FREERUN) list(APPEND SRCS stm32_freerun.c) endif() diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index b4078735ea7..ba432fccb42 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -1224,6 +1224,14 @@ config STM32_HAVE_COMMON_USBHOST_DEBUG config STM32_HAVE_USB bool +# LPTIM capabilities + +config STM32_HAVE_IP_LPTIM_V1 + bool + +config STM32_HAVE_IP_LPTIM_V2 + bool + # WDG capabilities config STM32_HAVE_IP_WDG_V1 diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index cda5d61fbae..6c6afc4fc98 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -107,6 +107,11 @@ endif ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c endif +ifeq ($(CONFIG_STM32_LPTIM),y) +ifneq ($(CONFIG_STM32_HAVE_IP_LPTIM_V1)$(CONFIG_STM32_HAVE_IP_LPTIM_V2),) +CHIP_CSRCS += stm32_lptim.c +endif +endif ifeq ($(CONFIG_STM32_FREERUN),y) CHIP_CSRCS += stm32_freerun.c endif diff --git a/arch/arm/src/stm32h5/hardware/stm32_lptim.h b/arch/arm/src/common/stm32/hardware/stm32_lptim.h similarity index 97% rename from arch/arm/src/stm32h5/hardware/stm32_lptim.h rename to arch/arm/src/common/stm32/hardware/stm32_lptim.h index 76f99394abc..d5150364d29 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_lptim.h +++ b/arch/arm/src/common/stm32/hardware/stm32_lptim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h5/hardware/stm32_lptim.h + * arch/arm/src/common/stm32/hardware/stm32_lptim.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_LPTIM_H -#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_LPTIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LPTIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LPTIM_H /**************************************************************************** * Included Files @@ -165,4 +165,4 @@ #define LPTIM_CFGR2_IN2SEL_SHIFT (4) /* Input 2 selection */ #define LPTIM_CFGR2_IN2SEL_MASK (3 << LPTIM_CFGR2_IN2SEL_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_LPTIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LPTIM_H */ diff --git a/arch/arm/src/stm32h5/stm32_lptim.c b/arch/arm/src/common/stm32/stm32_lptim.c similarity index 85% rename from arch/arm/src/stm32h5/stm32_lptim.c rename to arch/arm/src/common/stm32/stm32_lptim.c index 73318ce64f1..fcdf86a6a18 100644 --- a/arch/arm/src/stm32h5/stm32_lptim.c +++ b/arch/arm/src/common/stm32/stm32_lptim.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h5/stm32_lptim.c + * arch/arm/src/common/stm32/stm32_lptim.c * * SPDX-License-Identifier: Apache-2.0 * @@ -40,8 +40,8 @@ #include "chip.h" #include "arm_internal.h" #include "stm32_rcc.h" -#include "stm32_gpio.h" #include "stm32_lptim.h" +#include "stm32_lptim_clk.h" #if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) || \ defined(CONFIG_STM32_LPTIM3) || defined(CONFIG_STM32_LPTIM4) || \ @@ -170,6 +170,7 @@ static void stm32_lptim_setcfgr(struct stm32_lptim_dev_s *dev, static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, uint32_t period) { +#ifdef CONFIG_STM32_HAVE_IP_LPTIM_V2 uint32_t timeout; /* For STM32H5: Clear ARROK flag BEFORE writing ARR when timer is enabled @@ -180,9 +181,11 @@ static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, { stm32_putreg32(dev, STM32_LPTIM_ICR_OFFSET, LPTIM_ISR_ARROK); } +#endif stm32_putreg32(dev, STM32_LPTIM_ARR_OFFSET, period); +#ifdef CONFIG_STM32_HAVE_IP_LPTIM_V2 /* Wait for ARROK flag when timer is enabled */ if (stm32_getreg32(dev, STM32_LPTIM_CR_OFFSET) & LPTIM_CR_ENABLE) @@ -194,11 +197,13 @@ static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, timeout--; } } +#endif } static void stm32_lptim_setcompare(struct stm32_lptim_dev_s *dev, uint32_t cmp) { +#ifdef CONFIG_STM32_HAVE_IP_LPTIM_V2 uint32_t timeout; /* For STM32H5: Clear CMPOK flag BEFORE writing CMP when timer is enabled */ @@ -207,9 +212,11 @@ static void stm32_lptim_setcompare(struct stm32_lptim_dev_s *dev, { stm32_putreg32(dev, STM32_LPTIM_ICR_OFFSET, LPTIM_ISR_CMPOK); } +#endif stm32_putreg32(dev, STM32_LPTIM_CMP_OFFSET, cmp); +#ifdef CONFIG_STM32_HAVE_IP_LPTIM_V2 /* Wait for CMPOK flag when timer is enabled */ if (stm32_getreg32(dev, STM32_LPTIM_CR_OFFSET) & LPTIM_CR_ENABLE) @@ -221,6 +228,7 @@ static void stm32_lptim_setcompare(struct stm32_lptim_dev_s *dev, timeout--; } } +#endif } static uint32_t stm32_lptim_getcounter(struct stm32_lptim_dev_s *dev) @@ -251,6 +259,11 @@ static int stm32_lptim_setinput(struct stm32_lptim_dev_s *dev, { #ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: +#endif +#ifdef CONFIG_STM32_LPTIM2 + case STM32_LPTIM2_BASE: +#endif +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) if (input == 0) { modifyreg32(dev->base + STM32_LPTIM_CFGR2_OFFSET, @@ -437,34 +450,40 @@ struct stm32_lptim_dev_s *stm32_lptim_init(int lptimer) switch (lptimer) { -#ifdef CONFIG_STM32_LPTIM1 +#if defined(CONFIG_STM32_LPTIM1) && defined(STM32_RCC_LPTIM1_EN_REG) case 1: dev = &stm32_lptim1_priv; - modifyreg32(STM32_RCC_APB3ENR, 0, RCC_APB3ENR_LPTIM1EN); + modifyreg32(STM32_RCC_LPTIM1_EN_REG, 0, STM32_RCC_LPTIM1_EN); break; #endif -#ifdef CONFIG_STM32_LPTIM3 +#if defined(CONFIG_STM32_LPTIM2) && defined(STM32_RCC_LPTIM2_EN_REG) + case 2: + dev = &stm32_lptim2_priv; + modifyreg32(STM32_RCC_LPTIM2_EN_REG, 0, STM32_RCC_LPTIM2_EN); + break; +#endif +#if defined(CONFIG_STM32_LPTIM3) && defined(STM32_RCC_LPTIM3_EN_REG) case 3: dev = &stm32_lptim3_priv; - modifyreg32(STM32_RCC_APB3ENR, 0, RCC_APB3ENR_LPTIM3EN); + modifyreg32(STM32_RCC_LPTIM3_EN_REG, 0, STM32_RCC_LPTIM3_EN); break; #endif -#ifdef CONFIG_STM32_LPTIM4 +#if defined(CONFIG_STM32_LPTIM4) && defined(STM32_RCC_LPTIM4_EN_REG) case 4: dev = &stm32_lptim4_priv; - modifyreg32(STM32_RCC_APB3ENR, 0, RCC_APB3ENR_LPTIM4EN); + modifyreg32(STM32_RCC_LPTIM4_EN_REG, 0, STM32_RCC_LPTIM4_EN); break; #endif -#ifdef CONFIG_STM32_LPTIM5 +#if defined(CONFIG_STM32_LPTIM5) && defined(STM32_RCC_LPTIM5_EN_REG) case 5: dev = &stm32_lptim5_priv; - modifyreg32(STM32_RCC_APB3ENR, 0, RCC_APB3ENR_LPTIM5EN); + modifyreg32(STM32_RCC_LPTIM5_EN_REG, 0, STM32_RCC_LPTIM5_EN); break; #endif -#ifdef CONFIG_STM32_LPTIM6 +#if defined(CONFIG_STM32_LPTIM6) && defined(STM32_RCC_LPTIM6_EN_REG) case 6: dev = &stm32_lptim6_priv; - modifyreg32(STM32_RCC_APB3ENR, 0, RCC_APB3ENR_LPTIM6EN); + modifyreg32(STM32_RCC_LPTIM6_EN_REG, 0, STM32_RCC_LPTIM6_EN); break; #endif default: @@ -482,29 +501,34 @@ int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) switch (dev->base) { -#ifdef CONFIG_STM32_LPTIM1 +#if defined(CONFIG_STM32_LPTIM1) && defined(STM32_RCC_LPTIM1_EN_REG) case STM32_LPTIM1_BASE: - modifyreg32(STM32_RCC_APB3ENR, RCC_APB3ENR_LPTIM1EN, 0); + modifyreg32(STM32_RCC_LPTIM1_EN_REG, STM32_RCC_LPTIM1_EN, 0); break; #endif -#ifdef CONFIG_STM32_LPTIM3 +#if defined(CONFIG_STM32_LPTIM2) && defined(STM32_RCC_LPTIM2_EN_REG) + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_LPTIM2_EN_REG, STM32_RCC_LPTIM2_EN, 0); + break; +#endif +#if defined(CONFIG_STM32_LPTIM3) && defined(STM32_RCC_LPTIM3_EN_REG) case STM32_LPTIM3_BASE: - modifyreg32(STM32_RCC_APB3ENR, RCC_APB3ENR_LPTIM3EN, 0); + modifyreg32(STM32_RCC_LPTIM3_EN_REG, STM32_RCC_LPTIM3_EN, 0); break; #endif -#ifdef CONFIG_STM32_LPTIM4 +#if defined(CONFIG_STM32_LPTIM4) && defined(STM32_RCC_LPTIM4_EN_REG) case STM32_LPTIM4_BASE: - modifyreg32(STM32_RCC_APB3ENR, RCC_APB3ENR_LPTIM4EN, 0); + modifyreg32(STM32_RCC_LPTIM4_EN_REG, STM32_RCC_LPTIM4_EN, 0); break; #endif -#ifdef CONFIG_STM32_LPTIM5 +#if defined(CONFIG_STM32_LPTIM5) && defined(STM32_RCC_LPTIM5_EN_REG) case STM32_LPTIM5_BASE: - modifyreg32(STM32_RCC_APB3ENR, RCC_APB3ENR_LPTIM5EN, 0); + modifyreg32(STM32_RCC_LPTIM5_EN_REG, STM32_RCC_LPTIM5_EN, 0); break; #endif -#ifdef CONFIG_STM32_LPTIM6 +#if defined(CONFIG_STM32_LPTIM6) && defined(STM32_RCC_LPTIM6_EN_REG) case STM32_LPTIM6_BASE: - modifyreg32(STM32_RCC_APB3ENR, RCC_APB3ENR_LPTIM6EN, 0); + modifyreg32(STM32_RCC_LPTIM6_EN_REG, STM32_RCC_LPTIM6_EN, 0); break; #endif default: diff --git a/arch/arm/src/stm32h7/stm32_lptim.h b/arch/arm/src/common/stm32/stm32_lptim.h similarity index 94% rename from arch/arm/src/stm32h7/stm32_lptim.h rename to arch/arm/src/common/stm32/stm32_lptim.h index a6d7c4f4648..3ed2a3b736a 100644 --- a/arch/arm/src/stm32h7/stm32_lptim.h +++ b/arch/arm/src/common/stm32/stm32_lptim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h7/stm32_lptim.h + * arch/arm/src/common/stm32/stm32_lptim.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32H7_STM32_LPTIM_H -#define __ARCH_ARM_SRC_STM32H7_STM32_LPTIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_LPTIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_LPTIM_H /**************************************************************************** * Included Files @@ -103,4 +103,4 @@ int stm32_lptim_deinit(struct stm32_lptim_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32H7_STM32_LPTIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_LPTIM_H */ diff --git a/arch/arm/src/common/stm32/stm32_lptim_clk.h b/arch/arm/src/common/stm32/stm32_lptim_clk.h new file mode 100644 index 00000000000..e76915eff7e --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_lptim_clk.h @@ -0,0 +1,163 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_lptim_clk.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_LPTIM_CLK_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_LPTIM_CLK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RCC clock-enable and reset aliases for the common LPTIM driver. + * + * The bus of each LPTIM instance differs between families and is detected + * from the RCC bit definitions. APB3 is checked first, the STM32U5 RCC + * header also defines the STM32L4 APB1 LPTIM bits. The LPTIM kernel clock + * is provided by each board as STM32_LPTIMn_CLKIN. + */ + +#if defined(RCC_APB3ENR_LPTIM1EN) +# define STM32_RCC_LPTIM1_EN_REG STM32_RCC_APB3ENR +# define STM32_RCC_LPTIM1_EN RCC_APB3ENR_LPTIM1EN +# define STM32_RCC_LPTIM1_RST_REG STM32_RCC_APB3RSTR +# define STM32_RCC_LPTIM1_RST RCC_APB3RSTR_LPTIM1RST +#elif defined(RCC_APB1ENR1_LPTIM1EN) +# define STM32_RCC_LPTIM1_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_LPTIM1_EN RCC_APB1ENR1_LPTIM1EN +# define STM32_RCC_LPTIM1_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_LPTIM1_RST RCC_APB1RSTR1_LPTIM1RST +#elif defined(RCC_APB1LENR_LPTIM1EN) +# define STM32_RCC_LPTIM1_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_LPTIM1_EN RCC_APB1LENR_LPTIM1EN +# define STM32_RCC_LPTIM1_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_LPTIM1_RST RCC_APB1LRSTR_LPTIM1RST +#elif defined(RCC_APB1ENR_LPTIM1EN) +# define STM32_RCC_LPTIM1_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_LPTIM1_EN RCC_APB1ENR_LPTIM1EN +# define STM32_RCC_LPTIM1_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_LPTIM1_RST RCC_APB1RSTR_LPTIM1RST +#endif + +#if defined(RCC_APB1HENR_LPTIM2EN) +# define STM32_RCC_LPTIM2_EN_REG STM32_RCC_APB1HENR +# define STM32_RCC_LPTIM2_EN RCC_APB1HENR_LPTIM2EN +# define STM32_RCC_LPTIM2_RST_REG STM32_RCC_APB1HRSTR +# define STM32_RCC_LPTIM2_RST RCC_APB1HRSTR_LPTIM2RST +#elif defined(RCC_APB4ENR_LPTIM2EN) +# define STM32_RCC_LPTIM2_EN_REG STM32_RCC_APB4ENR +# define STM32_RCC_LPTIM2_EN RCC_APB4ENR_LPTIM2EN +# define STM32_RCC_LPTIM2_RST_REG STM32_RCC_APB4RSTR +# define STM32_RCC_LPTIM2_RST RCC_APB4RSTR_LPTIM2RST +#elif defined(RCC_APB4LENR_LPTIM2EN) +# define STM32_RCC_LPTIM2_EN_REG STM32_RCC_APB4LENR +# define STM32_RCC_LPTIM2_EN RCC_APB4LENR_LPTIM2EN +# define STM32_RCC_LPTIM2_RST_REG STM32_RCC_APB4LRSTR +# define STM32_RCC_LPTIM2_RST RCC_APB4LRSTR_LPTIM2RST +#elif defined(RCC_APB1ENR2_LPTIM2EN) +# define STM32_RCC_LPTIM2_EN_REG STM32_RCC_APB1ENR2 +# define STM32_RCC_LPTIM2_EN RCC_APB1ENR2_LPTIM2EN +# define STM32_RCC_LPTIM2_RST_REG STM32_RCC_APB1RSTR2 +# define STM32_RCC_LPTIM2_RST RCC_APB1RSTR2_LPTIM2RST +#elif defined(RCC_APB1ENR_LPTIM2EN) +# define STM32_RCC_LPTIM2_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_LPTIM2_EN RCC_APB1ENR_LPTIM2EN +# define STM32_RCC_LPTIM2_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_LPTIM2_RST RCC_APB1RSTR_LPTIM2RST +#endif + +#if defined(RCC_APB3ENR_LPTIM3EN) +# define STM32_RCC_LPTIM3_EN_REG STM32_RCC_APB3ENR +# define STM32_RCC_LPTIM3_EN RCC_APB3ENR_LPTIM3EN +# define STM32_RCC_LPTIM3_RST_REG STM32_RCC_APB3RSTR +# define STM32_RCC_LPTIM3_RST RCC_APB3RSTR_LPTIM3RST +#elif defined(RCC_APB4ENR_LPTIM3EN) +# define STM32_RCC_LPTIM3_EN_REG STM32_RCC_APB4ENR +# define STM32_RCC_LPTIM3_EN RCC_APB4ENR_LPTIM3EN +# define STM32_RCC_LPTIM3_RST_REG STM32_RCC_APB4RSTR +# define STM32_RCC_LPTIM3_RST RCC_APB4RSTR_LPTIM3RST +#elif defined(RCC_APB4LENR_LPTIM3EN) +# define STM32_RCC_LPTIM3_EN_REG STM32_RCC_APB4LENR +# define STM32_RCC_LPTIM3_EN RCC_APB4LENR_LPTIM3EN +# define STM32_RCC_LPTIM3_RST_REG STM32_RCC_APB4LRSTR +# define STM32_RCC_LPTIM3_RST RCC_APB4LRSTR_LPTIM3RST +#elif defined(RCC_APB1ENR2_LPTIM3EN) +# define STM32_RCC_LPTIM3_EN_REG STM32_RCC_APB1ENR2 +# define STM32_RCC_LPTIM3_EN RCC_APB1ENR2_LPTIM3EN +# define STM32_RCC_LPTIM3_RST_REG STM32_RCC_APB1RSTR2 +# define STM32_RCC_LPTIM3_RST RCC_APB1RSTR2_LPTIM3RST +#elif defined(RCC_APB1ENR_LPTIM3EN) +# define STM32_RCC_LPTIM3_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_LPTIM3_EN RCC_APB1ENR_LPTIM3EN +# define STM32_RCC_LPTIM3_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_LPTIM3_RST RCC_APB1RSTR_LPTIM3RST +#endif + +#if defined(RCC_APB3ENR_LPTIM4EN) +# define STM32_RCC_LPTIM4_EN_REG STM32_RCC_APB3ENR +# define STM32_RCC_LPTIM4_EN RCC_APB3ENR_LPTIM4EN +# define STM32_RCC_LPTIM4_RST_REG STM32_RCC_APB3RSTR +# define STM32_RCC_LPTIM4_RST RCC_APB3RSTR_LPTIM4RST +#elif defined(RCC_APB4ENR_LPTIM4EN) +# define STM32_RCC_LPTIM4_EN_REG STM32_RCC_APB4ENR +# define STM32_RCC_LPTIM4_EN RCC_APB4ENR_LPTIM4EN +# define STM32_RCC_LPTIM4_RST_REG STM32_RCC_APB4RSTR +# define STM32_RCC_LPTIM4_RST RCC_APB4RSTR_LPTIM4RST +#elif defined(RCC_APB4LENR_LPTIM4EN) +# define STM32_RCC_LPTIM4_EN_REG STM32_RCC_APB4LENR +# define STM32_RCC_LPTIM4_EN RCC_APB4LENR_LPTIM4EN +# define STM32_RCC_LPTIM4_RST_REG STM32_RCC_APB4LRSTR +# define STM32_RCC_LPTIM4_RST RCC_APB4LRSTR_LPTIM4RST +#endif + +#if defined(RCC_APB3ENR_LPTIM5EN) +# define STM32_RCC_LPTIM5_EN_REG STM32_RCC_APB3ENR +# define STM32_RCC_LPTIM5_EN RCC_APB3ENR_LPTIM5EN +# define STM32_RCC_LPTIM5_RST_REG STM32_RCC_APB3RSTR +# define STM32_RCC_LPTIM5_RST RCC_APB3RSTR_LPTIM5RST +#elif defined(RCC_APB4ENR_LPTIM5EN) +# define STM32_RCC_LPTIM5_EN_REG STM32_RCC_APB4ENR +# define STM32_RCC_LPTIM5_EN RCC_APB4ENR_LPTIM5EN +# define STM32_RCC_LPTIM5_RST_REG STM32_RCC_APB4RSTR +# define STM32_RCC_LPTIM5_RST RCC_APB4RSTR_LPTIM5RST +#elif defined(RCC_APB4LENR_LPTIM5EN) +# define STM32_RCC_LPTIM5_EN_REG STM32_RCC_APB4LENR +# define STM32_RCC_LPTIM5_EN RCC_APB4LENR_LPTIM5EN +# define STM32_RCC_LPTIM5_RST_REG STM32_RCC_APB4LRSTR +# define STM32_RCC_LPTIM5_RST RCC_APB4LRSTR_LPTIM5RST +#endif + +#if defined(RCC_APB3ENR_LPTIM6EN) +# define STM32_RCC_LPTIM6_EN_REG STM32_RCC_APB3ENR +# define STM32_RCC_LPTIM6_EN RCC_APB3ENR_LPTIM6EN +# define STM32_RCC_LPTIM6_RST_REG STM32_RCC_APB3RSTR +# define STM32_RCC_LPTIM6_RST RCC_APB3RSTR_LPTIM6RST +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_LPTIM_CLK_H */ diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt index 1284ecfa936..0e422b4db86 100644 --- a/arch/arm/src/stm32h5/CMakeLists.txt +++ b/arch/arm/src/stm32h5/CMakeLists.txt @@ -72,10 +72,6 @@ if(CONFIG_STM32_QSPI1) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32_LPTIM) - list(APPEND SRCS stm32_lptim.c) -endif() - if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32_hsi48.c) endif() diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index a3236fdbdae..090f87e0a50 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -15,6 +15,7 @@ config STM32_H5_PERIPHERALS select STM32_HAVE_IP_GPIO_M33_V1 select STM32_HAVE_IP_TIMERS_V3 select STM32_HAVE_IP_DBGMCU_V5 + select STM32_HAVE_IP_LPTIM_V2 select STM32_HAVE_IP_USART_M33_V3 select STM32_HAVE_DMA1 select STM32_HAVE_DMA2 diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs index 1c620a10773..a598a5dd01a 100644 --- a/arch/arm/src/stm32h5/Make.defs +++ b/arch/arm/src/stm32h5/Make.defs @@ -80,10 +80,6 @@ ifeq ($(CONFIG_STM32_QSPI1),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32_LPTIM),y) -CHIP_CSRCS += stm32_lptim.c -endif - ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32_hsi48.c endif diff --git a/arch/arm/src/stm32h5/stm32_lptim.h b/arch/arm/src/stm32h5/stm32_lptim.h deleted file mode 100644 index 913117f31a4..00000000000 --- a/arch/arm/src/stm32h5/stm32_lptim.h +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_lptim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_STM32_LPTIM_H -#define __ARCH_ARM_SRC_STM32H5_STM32_LPTIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include "chip.h" -#include "hardware/stm32_lptim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#if defined(__cplusplus) -extern "C" -{ -#endif - -typedef enum -{ - STM32_LPTIM_MODE_CONTINUOUS = 0x00, - STM32_LPTIM_MODE_SINGLE = 0x01 -} stm32_lptim_start_mode_t; - -/* LPTIM Device Structure */ - -struct stm32_lptim_dev_s -{ - const struct stm32_lptim_ops_s *ops; - uint32_t base; -}; - -/* LPTIM Operations */ - -struct stm32_lptim_ops_s -{ - void (*setcfgr)(struct stm32_lptim_dev_s *dev, uint32_t regval); - void (*setperiod)(struct stm32_lptim_dev_s *dev, uint32_t period); - void (*setcompare)(struct stm32_lptim_dev_s *dev, uint32_t cmp); - uint32_t (*getcounter)(struct stm32_lptim_dev_s *dev); - int (*setinput)(struct stm32_lptim_dev_s *dev, uint32_t input, - uint32_t mux); - void (*enable)(struct stm32_lptim_dev_s *dev, bool on); - void (*start)(struct stm32_lptim_dev_s *dev, - stm32_lptim_start_mode_t mode); - void (*resetcounter)(struct stm32_lptim_dev_s *dev); - void (*enablerar)(struct stm32_lptim_dev_s *dev, bool on); - - /* Low-power timer interrupts */ - - int (*setisr)(struct stm32_lptim_dev_s *dev, xcpt_t handler, - void *arg, int source); - void (*enableint)(struct stm32_lptim_dev_s *dev, int source); - void (*disableint)(struct stm32_lptim_dev_s *dev, int source); - void (*ackint)(struct stm32_lptim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up low power timer and get its structure */ - -struct stm32_lptim_dev_s *stm32_lptim_init(int lptimer); - -/* Power-down low power timer, mark it as unused */ - -int stm32_lptim_deinit(struct stm32_lptim_dev_s *dev); - -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32H5_STM32_LPTIM_H */ diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index 0243ccaa07e..d017f53ee7c 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -162,10 +162,6 @@ if(CONFIG_USBHOST) endif() endif() -if(CONFIG_STM32_LPTIM) - list(APPEND SRCS stm32_lptim.c) -endif() - if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 5b1cb407b99..c396e1da7e4 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -19,6 +19,7 @@ config STM32_H7_LEGACY default n select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_IP_WDG_V2 + select STM32_HAVE_IP_LPTIM_V1 select STM32_HAVE_EXTI_SHARED_IRQ select STM32_HAVE_DMA1 select STM32_HAVE_DMA2 @@ -826,6 +827,7 @@ config STM32_STM32H7RSXX default n select STM32_HAVE_IP_TIMERS_V3 select STM32_HAVE_IP_WDG_V3 + select STM32_HAVE_IP_LPTIM_V2 select STM32_H7_BOOTFLASH select STM32_HAVE_XSPI select STM32_HAVE_SBS diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 5fbbdb83880..fc03647a89e 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -165,10 +165,6 @@ endif endif endif -ifeq ($(CONFIG_STM32_LPTIM),y) -CHIP_CSRCS += stm32_lptim.c -endif - ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif diff --git a/arch/arm/src/stm32h7/hardware/stm32_lptim.h b/arch/arm/src/stm32h7/hardware/stm32_lptim.h deleted file mode 100644 index a0fe9ee9ab6..00000000000 --- a/arch/arm/src/stm32h7/hardware/stm32_lptim.h +++ /dev/null @@ -1,178 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/hardware/stm32_lptim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_LPTIM_H -#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_LPTIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and status register */ -#define STM32_LPTIM_ICR_OFFSET 0x0004 /* Interrupt clear register */ -#define STM32_LPTIM_IER_OFFSET 0x0008 /* Interrupt enable register */ -#define STM32_LPTIM_CFGR_OFFSET 0x000C /* Configuration register */ -#define STM32_LPTIM_CR_OFFSET 0x0010 /* Control register */ -#define STM32_LPTIM_CMP_OFFSET 0x0014 /* Compare register */ -#define STM32_LPTIM_ARR_OFFSET 0x0018 /* Autoreloar register */ -#define STM32_LPTIM_CNT_OFFSET 0x001C /* Counter register */ -#define STM32_LPTIM_CFGR2_OFFSET 0x0024 /* Configuration register 2 */ - -/* Register Addresses *******************************************************/ - -# define STM32_LPTIM1_ISR (STM32_LPTIM1_BASE+STM32_LPTIM_ISR_OFFSET) -# define STM32_LPTIM1_ICR (STM32_LPTIM1_BASE+STM32_LPTIM_ICR_OFFSET) -# define STM32_LPTIM1_IER (STM32_LPTIM1_BASE+STM32_LPTIM_IER_OFFSET) -# define STM32_LPTIM1_CFGR (STM32_LPTIM1_BASE+STM32_LPTIM_CFGR_OFFSET) -# define STM32_LPTIM1_CR (STM32_LPTIM1_BASE+STM32_LPTIM_CR_OFFSET) -# define STM32_LPTIM1_CMP (STM32_LPTIM1_BASE+STM32_LPTIM_CMP_OFFSET) -# define STM32_LPTIM1_ARR (STM32_LPTIM1_BASE+STM32_LPTIM_ARR_OFFSET) -# define STM32_LPTIM1_CNT (STM32_LPTIM1_BASE+STM32_LPTIM_CNT_OFFSET) -# define STM32_LPTIM1_CFGR2 (STM32_LPTIM1_BASE+STM32_LPTIM_CFGR2_OFFSET) - -# define STM32_LPTIM2_ISR (STM32_LPTIM2_BASE+STM32_LPTIM_ISR_OFFSET) -# define STM32_LPTIM2_ICR (STM32_LPTIM2_BASE+STM32_LPTIM_ICR_OFFSET) -# define STM32_LPTIM2_IER (STM32_LPTIM2_BASE+STM32_LPTIM_IER_OFFSET) -# define STM32_LPTIM2_CFGR (STM32_LPTIM2_BASE+STM32_LPTIM_CFGR_OFFSET) -# define STM32_LPTIM2_CR (STM32_LPTIM2_BASE+STM32_LPTIM_CR_OFFSET) -# define STM32_LPTIM2_CMP (STM32_LPTIM2_BASE+STM32_LPTIM_CMP_OFFSET) -# define STM32_LPTIM2_ARR (STM32_LPTIM2_BASE+STM32_LPTIM_ARR_OFFSET) -# define STM32_LPTIM2_CNT (STM32_LPTIM2_BASE+STM32_LPTIM_CNT_OFFSET) -# define STM32_LPTIM2_CFGR2 (STM32_LPTIM2_BASE+STM32_LPTIM_CFGR2_OFFSET) - -# define STM32_LPTIM3_ISR (STM32_LPTIM3_BASE+STM32_LPTIM_ISR_OFFSET) -# define STM32_LPTIM3_ICR (STM32_LPTIM3_BASE+STM32_LPTIM_ICR_OFFSET) -# define STM32_LPTIM3_IER (STM32_LPTIM3_BASE+STM32_LPTIM_IER_OFFSET) -# define STM32_LPTIM3_CFGR (STM32_LPTIM3_BASE+STM32_LPTIM_CFGR_OFFSET) -# define STM32_LPTIM3_CR (STM32_LPTIM3_BASE+STM32_LPTIM_CR_OFFSET) -# define STM32_LPTIM3_CMP (STM32_LPTIM3_BASE+STM32_LPTIM_CMP_OFFSET) -# define STM32_LPTIM3_ARR (STM32_LPTIM3_BASE+STM32_LPTIM_ARR_OFFSET) -# define STM32_LPTIM3_CNT (STM32_LPTIM3_BASE+STM32_LPTIM_CNT_OFFSET) -# define STM32_LPTIM3_CFGR2 (STM32_LPTIM3_BASE+STM32_LPTIM_CFGR2_OFFSET) - -# define STM32_LPTIM4_ISR (STM32_LPTIM4_BASE+STM32_LPTIM_ISR_OFFSET) -# define STM32_LPTIM4_ICR (STM32_LPTIM4_BASE+STM32_LPTIM_ICR_OFFSET) -# define STM32_LPTIM4_IER (STM32_LPTIM4_BASE+STM32_LPTIM_IER_OFFSET) -# define STM32_LPTIM4_CFGR (STM32_LPTIM4_BASE+STM32_LPTIM_CFGR_OFFSET) -# define STM32_LPTIM4_CR (STM32_LPTIM4_BASE+STM32_LPTIM_CR_OFFSET) -# define STM32_LPTIM4_CMP (STM32_LPTIM4_BASE+STM32_LPTIM_CMP_OFFSET) -# define STM32_LPTIM4_ARR (STM32_LPTIM4_BASE+STM32_LPTIM_ARR_OFFSET) -# define STM32_LPTIM4_CNT (STM32_LPTIM4_BASE+STM32_LPTIM_CNT_OFFSET) -# define STM32_LPTIM4_CFGR2 (STM32_LPTIM4_BASE+STM32_LPTIM_CFGR2_OFFSET) - -# define STM32_LPTIM5_ISR (STM32_LPTIM5_BASE+STM32_LPTIM_ISR_OFFSET) -# define STM32_LPTIM5_ICR (STM32_LPTIM5_BASE+STM32_LPTIM_ICR_OFFSET) -# define STM32_LPTIM5_IER (STM32_LPTIM5_BASE+STM32_LPTIM_IER_OFFSET) -# define STM32_LPTIM5_CFGR (STM32_LPTIM5_BASE+STM32_LPTIM_CFGR_OFFSET) -# define STM32_LPTIM5_CR (STM32_LPTIM5_BASE+STM32_LPTIM_CR_OFFSET) -# define STM32_LPTIM5_CMP (STM32_LPTIM5_BASE+STM32_LPTIM_CMP_OFFSET) -# define STM32_LPTIM5_ARR (STM32_LPTIM5_BASE+STM32_LPTIM_ARR_OFFSET) -# define STM32_LPTIM5_CNT (STM32_LPTIM5_BASE+STM32_LPTIM_CNT_OFFSET) -# define STM32_LPTIM5_CFGR2 (STM32_LPTIM5_BASE+STM32_LPTIM_CFGR2_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Interrupt flags for ISR, ICR and IER */ - -#define LPTIM_IxR_CMPM (1 << 0) /* Bit 0: Compare match */ -#define LPTIM_IxR_ARRM (1 << 1) /* Bit 1: Autoreload match */ -#define LPTIM_IxR_EXTTRIG (1 << 2) /* Bit 2: External trigger edge event */ -#define LPTIM_IxR_CMPOK (1 << 3) /* Bit 3: Compare register update OK */ -#define LPTIM_IxR_ARROK (1 << 4) /* Bit 4: Autoreload register update OK */ -#define LPTIM_IxR_UP (1 << 5) /* Bit 5: Counter direction change down to up */ -#define LPTIM_IxR_DOWN (1 << 6) /* Bit 6: Counter direction change up to down */ - -/* Configuration register */ - -#define LPTIM_CFGR_CKSEL (1 << 0) /* Bit 0: Clock selector */ -#define LPTIM_CFGR_CKPOL_SHIFT (1) /* Bits 1-2: Clock polarity */ -#define LPTIM_CFGR_CKPOL_MASK (3 << LPTIM_CFGR_CKPOL_SHIFT) -# define LPTIM_CFGR_CKPOL_RISE (0 << LPTIM_CFGR_CKPOL_SHIFT) /* 00: Rising edge */ -# define LPTIM_CFGR_CKPOL_FALL (1 << LPTIM_CFGR_CKPOL_SHIFT) /* 01: Falling edge */ -# define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT) /* 10: Both edges */ - -#define LPTIM_CFGR_CKFLT_SHIFT (3) /* Bits 3-4: Digital filter for clock*/ -#define LPTIM_CFGR_CKFLT_MASK (3 << LPTIM_CFGR_CKFLT_SHIFT) -# define LPTIM_CFGR_CKFLT_ANY (0 << LPTIM_CFGR_CKFLT_SHIFT) /* 00: Any */ -# define LPTIM_CFGR_CKFLT_2 (1 << LPTIM_CFGR_CKFLT_SHIFT) /* 01: 2 clocks */ -# define LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT) /* 10: 4 clocks */ -# define LPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT) /* 11: 8 clocks */ - -#define LPTIM_CFGR_TRGFLT_SHIFT (6) /* Bits 6-7: digital filter for trigger */ -#define LPTIM_CFGR_TRGFLT_MASK (3 << LPTIM_CFGR_TRGFLT_SHIFT) -# define LPTIM_CFGR_TRGFLT_ANY (0 << LPTIM_CFGR_TRGFLT_SHIFT) /* 00: Any */ -# define LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT) /* 01: 2 clocks */ -# define LPTIM_CFGR_TRGFLT_4 (2 << LPTIM_CFGR_TRGFLT_SHIFT) /* 10: 4 clocks */ -# define LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT) /* 11: 8 clocks */ - -#define LPTIM_CFGR_PRESC_SHIFT (9) /* Bits 9-11: Clock prescaler */ -#define LPTIM_CFGR_PRESC_MASK (7 << LPTIM_CFGR_PRESC_SHIFT) -# define LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT) -# define LPTIM_CFGR_PRESC_2 (1 << LPTIM_CFGR_PRESC_SHIFT) -# define LPTIM_CFGR_PRESC_4 (2 << LPTIM_CFGR_PRESC_SHIFT) -# define LPTIM_CFGR_PRESC_8 (3 << LPTIM_CFGR_PRESC_SHIFT) -# define LPTIM_CFGR_PRESC_16 (4 << LPTIM_CFGR_PRESC_SHIFT) -# define LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT) -# define LPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT) -# define LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT) - -#define LPTIM_CFGR_TRIGSEL_SHIFT (13) /* Bits 13-15: Trigger selector */ -#define LPTIM_CFGR_TRIGSEL_MASK (7 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGEN_SHIFT (17) /* Bits 17-18: Trigger enable and polarity */ -#define LPTIM_CFGR_TRIGEN_MASK (3 << LPTIM_CFGR_TRIGEN_SHIFT) -# define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT) /* 00: software */ -# define LPTIM_CFGR_TRIGEN_RISE (1 << LPTIM_CFGR_TRIGEN_SHIFT) /* 01: rising edge */ -# define LPTIM_CFGR_TRIGEN_FALL (2 << LPTIM_CFGR_TRIGEN_SHIFT) /* 10: falling edge */ -# define LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT) /* 11: both edges */ - -#define LPTIM_CFGR_TIMEOUT (1 << 19) /* Bit 19: Timeout enable */ -#define LPTIM_CFGR_WAVE (1 << 20) /* Bit 20: Waveform shape */ -#define LPTIM_CFGR_WAVPOL (1 << 21) /* Bit 21: Waveform shape polarity */ -#define LPTIM_CFGR_PRELOAD (1 << 22) /* Bit 22: Registers update mode */ -#define LPTIM_CFGR_COUNTMODE (1 << 23) /* Bit 23: Counter mode enable */ -#define LPTIM_CFGR_ENC (1 << 24) /* Bit 24: Encoder mode enable */ - -/* Control register */ - -#define LPTIM_CR_ENABLE (1 << 0) /* Bit 0: Enable */ -#define LPTIM_CR_SNGSTRT (1 << 1) /* Bit 1: Start in single mode */ -#define LPTIM_CR_CNTSTRT (1 << 2) /* Bit 2: Start in continuous mode */ -#define LPTIM_CR_COUNTRST (1 << 3) /* Bit 3: Counter reset */ -#define LPTIM_CR_RSTARE (1 << 4) /* Reset after read enable */ - -/* Configuration register 2 */ - -#define LPTIM_CFGR2_IN1SEL_SHIFT (0) /* Input 1 selection */ -#define LPTIM_CFGR2_IN1SEL_MASK (3 << LPTIM_CFGR2_IN1SEL_SHIFT) -#define LPTIM_CFGR2_IN2SEL_SHIFT (4) /* Input 2 selection */ -#define LPTIM_CFGR2_IN2SEL_MASK (3 << LPTIM_CFGR2_IN2SEL_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_LPTIM_H */ diff --git a/arch/arm/src/stm32h7/stm32_lptim.c b/arch/arm/src/stm32h7/stm32_lptim.c deleted file mode 100644 index 958243f7631..00000000000 --- a/arch/arm/src/stm32h7/stm32_lptim.c +++ /dev/null @@ -1,471 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_lptim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> -#include <nuttx/arch.h> -#include <nuttx/irq.h> - -#include <sys/types.h> -#include <stdint.h> -#include <stdbool.h> -#include <assert.h> -#include <errno.h> -#include <nuttx/debug.h> - -#include <arch/board/board.h> - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_lptim.h" - -#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) || \ - defined(CONFIG_STM32_LPTIM3) || defined(CONFIG_STM32_LPTIM4) || \ - defined(CONFIG_STM32_LPTIM5) - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Low-power timer methods */ - -static void stm32_lptim_setcfgr(struct stm32_lptim_dev_s *dev, - uint32_t regval); -static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, - uint32_t period); -static void stm32_lptim_setcompare(struct stm32_lptim_dev_s *dev, - uint32_t cmp); -static uint32_t stm32_lptim_getcounter(struct stm32_lptim_dev_s *dev); -static int stm32_lptim_setinput(struct stm32_lptim_dev_s *dev, - uint32_t input, uint32_t mux); -static void stm32_lptim_enable(struct stm32_lptim_dev_s *dev, bool on); -static void stm32_lptim_start(struct stm32_lptim_dev_s *dev, - stm32_lptim_start_mode_t mode); -static void stm32_lptim_resetcounter(struct stm32_lptim_dev_s *dev); -static void stm32_lptim_enablerar(struct stm32_lptim_dev_s *dev, - bool on); - -static int stm32_lptim_setisr(struct stm32_lptim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_lptim_enableint(struct stm32_lptim_dev_s *dev, - int source); -static void stm32_lptim_disableint(struct stm32_lptim_dev_s *dev, - int source); -static void stm32_lptim_ackint(struct stm32_lptim_dev_s *dev, - int source); - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_lptim_ops_s stm32_lptim_ops = -{ - .setcfgr = &stm32_lptim_setcfgr, - .setperiod = &stm32_lptim_setperiod, - .setcompare = &stm32_lptim_setcompare, - .getcounter = &stm32_lptim_getcounter, - .setinput = &stm32_lptim_setinput, - .enable = &stm32_lptim_enable, - .start = &stm32_lptim_start, - .resetcounter = &stm32_lptim_resetcounter, - .enablerar = &stm32_lptim_enablerar, - .setisr = &stm32_lptim_setisr, - .enableint = &stm32_lptim_enableint, - .disableint = &stm32_lptim_disableint, - .ackint = &stm32_lptim_ackint -}; - -#ifdef CONFIG_STM32_LPTIM1 -struct stm32_lptim_dev_s stm32_lptim1_priv = -{ - .ops = &stm32_lptim_ops, - .base = STM32_LPTIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_LPTIM2 -struct stm32_lptim_dev_s stm32_lptim2_priv = -{ - .ops = &stm32_lptim_ops, - .base = STM32_LPTIM2_BASE, -}; -#endif -#ifdef CONFIG_STM32_LPTIM3 -struct stm32_lptim_dev_s stm32_lptim3_priv = -{ - .ops = &stm32_lptim_ops, - .base = STM32_LPTIM3_BASE, -}; -#endif -#ifdef CONFIG_STM32_LPTIM4 -struct stm32_lptim_dev_s stm32_lptim4_priv = -{ - .ops = &stm32_lptim_ops, - .base = STM32_LPTIM4_BASE, -}; -#endif -#ifdef CONFIG_STM32_LPTIM5 -struct stm32_lptim_dev_s stm32_lptim5_priv = -{ - .ops = &stm32_lptim_ops, - .base = STM32_LPTIM5_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get a 32-bit register value by offset. - */ - -static inline uint32_t stm32_getreg32(struct stm32_lptim_dev_s *dev, - uint8_t offset) -{ - return getreg32(dev->base + offset); -} - -/* Put a 32-bit register value by offset. - */ - -static inline void stm32_putreg32(struct stm32_lptim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, dev->base + offset); -} - -static void stm32_lptim_setcfgr(struct stm32_lptim_dev_s *dev, - uint32_t regval) -{ - stm32_putreg32(dev, STM32_LPTIM_CFGR_OFFSET, regval); -} - -static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, - uint32_t period) -{ - stm32_putreg32(dev, STM32_LPTIM_ARR_OFFSET, period); -} - -static void stm32_lptim_setcompare(struct stm32_lptim_dev_s *dev, - uint32_t cmp) -{ - stm32_putreg32(dev, STM32_LPTIM_CMP_OFFSET, cmp); -} - -static uint32_t stm32_lptim_getcounter(struct stm32_lptim_dev_s *dev) -{ - /* For a reliable LPTIM_CNT register read access, two consecutive - * read accesses must be performed and compared - */ - - uint32_t cnt1; - uint32_t cnt2; - - cnt2 = stm32_getreg32(dev, STM32_LPTIM_CNT_OFFSET); - - do - { - cnt1 = cnt2; - cnt2 = stm32_getreg32(dev, STM32_LPTIM_CNT_OFFSET); - } - while (cnt1 != cnt2); - - return cnt1; -} - -static int stm32_lptim_setinput(struct stm32_lptim_dev_s *dev, - uint32_t input, uint32_t mux) -{ - switch (dev->base) - { -#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) - case STM32_LPTIM1_BASE: - case STM32_LPTIM2_BASE: - if (input == 0) - { - modifyreg32(dev->base + STM32_LPTIM_CFGR2_OFFSET, - LPTIM_CFGR2_IN1SEL_MASK, mux); - } - else - { - modifyreg32(dev->base + STM32_LPTIM_CFGR2_OFFSET, - LPTIM_CFGR2_IN2SEL_MASK, - mux << LPTIM_CFGR2_IN2SEL_SHIFT); - } - break; -#endif -#ifdef CONFIG_STM32_LPTIM3 - case STM32_LPTIM3_BASE: - modifyreg32(dev->base + STM32_LPTIM_CFGR2_OFFSET, - LPTIM_CFGR2_IN1SEL_MASK, mux); - break; -#endif - default: - return -EINVAL; - } - - return OK; -} - -static void stm32_lptim_enable(struct stm32_lptim_dev_s *dev, bool on) -{ - uint32_t val = stm32_getreg32(dev, STM32_LPTIM_CR_OFFSET); - - if (on) - { - val |= LPTIM_CR_ENABLE; - } - else - { - val &= ~LPTIM_CR_ENABLE; - } - - stm32_putreg32(dev, STM32_LPTIM_CR_OFFSET, val); -} - -static void stm32_lptim_start(struct stm32_lptim_dev_s *dev, - stm32_lptim_start_mode_t mode) -{ - uint32_t val = stm32_getreg32(dev, STM32_LPTIM_CR_OFFSET); - - switch (mode) - { - case STM32_LPTIM_MODE_CONTINUOUS: - val |= LPTIM_CR_CNTSTRT; - break; - case STM32_LPTIM_MODE_SINGLE: - val |= LPTIM_CR_SNGSTRT; - break; - } - - stm32_putreg32(dev, STM32_LPTIM_CR_OFFSET, val); -} - -static void stm32_lptim_resetcounter(struct stm32_lptim_dev_s *dev) -{ - uint32_t val = stm32_getreg32(dev, STM32_LPTIM_CR_OFFSET); - val |= LPTIM_CR_COUNTRST; - stm32_putreg32(dev, STM32_LPTIM_CR_OFFSET, val); -} - -static void stm32_lptim_enablerar(struct stm32_lptim_dev_s *dev, bool on) -{ - uint32_t val = stm32_getreg32(dev, STM32_LPTIM_CR_OFFSET); - - if (on) - { - val |= LPTIM_CR_RSTARE; - } - else - { - val &= ~LPTIM_CR_RSTARE; - } - - stm32_putreg32(dev, STM32_LPTIM_CR_OFFSET, val); -} - -static int stm32_lptim_setisr(struct stm32_lptim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (dev->base) - { -#ifdef CONFIG_STM32_LPTIM1 - case STM32_LPTIM1_BASE: - vectorno = STM32_IRQ_LPTIM1; - break; -#endif -#ifdef CONFIG_STM32_LPTIM2 - case STM32_LPTIM2_BASE: - vectorno = STM32_IRQ_LPTIM2; - break; -#endif -#ifdef CONFIG_STM32_LPTIM3 - case STM32_LPTIM3_BASE: - vectorno = STM32_IRQ_LPTIM3; - break; -#endif -#ifdef CONFIG_STM32_LPTIM4 - case STM32_LPTIM4_BASE: - vectorno = STM32_IRQ_LPTIM4; - break; -#endif -#ifdef CONFIG_STM32_LPTIM5 - case STM32_LPTIM5_BASE: - vectorno = STM32_IRQ_LPTIM5; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - - return OK; -} - -static void stm32_lptim_enableint(struct stm32_lptim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - - uint32_t val = stm32_getreg32(dev, STM32_LPTIM_IER_OFFSET); - val |= source; - stm32_putreg32(dev, STM32_LPTIM_IER_OFFSET, val); -} - -static void stm32_lptim_disableint(struct stm32_lptim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - - uint32_t val = stm32_getreg32(dev, STM32_LPTIM_IER_OFFSET); - val &= ~source; - stm32_putreg32(dev, STM32_LPTIM_IER_OFFSET, val); -} - -static void stm32_lptim_ackint(struct stm32_lptim_dev_s *dev, int source) -{ - stm32_putreg32(dev, STM32_LPTIM_ICR_OFFSET, source); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct stm32_lptim_dev_s *stm32_lptim_init(int lptimer) -{ - struct stm32_lptim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (lptimer) - { -#ifdef CONFIG_STM32_LPTIM1 - case 1: - dev = &stm32_lptim1_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_LPTIM1EN); - break; -#endif -#ifdef CONFIG_STM32_LPTIM2 - case 2: - dev = &stm32_lptim2_priv; - modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM2EN); - break; -#endif -#ifdef CONFIG_STM32_LPTIM3 - case 3: - dev = &stm32_lptim3_priv; - modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM3EN); - break; -#endif -#ifdef CONFIG_STM32_LPTIM4 - case 4: - dev = &stm32_lptim4_priv; - modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM4EN); - break; -#endif -#ifdef CONFIG_STM32_LPTIM5 - case 5: - dev = &stm32_lptim5_priv; - modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM5EN); - break; -#endif - default: - return NULL; - } - - return dev; -} - -int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (dev->base) - { -#ifdef CONFIG_STM32_LPTIM1 - case STM32_LPTIM1_BASE: - modifyreg32(STM32_RCC_APB1LLPENR, RCC_APB1LENR_LPTIM1EN, 0); - break; -#endif -#ifdef CONFIG_STM32_LPTIM2 - case STM32_LPTIM2_BASE: - modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM2EN, 0); - break; -#endif -#ifdef CONFIG_STM32_LPTIM3 - case STM32_LPTIM3_BASE: - modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM3EN, 0); - break; -#endif -#ifdef CONFIG_STM32_LPTIM4 - case STM32_LPTIM4_BASE: - modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM4EN, 0); - break; -#endif -#ifdef CONFIG_STM32_LPTIM5 - case STM32_LPTIM5_BASE: - modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM5EN, 0); - break; -#endif - default: - return -EINVAL; - } - - return OK; -} - -#endif /* defined(CONFIG_STM32_LPTIM1 || ... || CONFIG_STM32_LPTIM5) */
