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commit 70e9f0fd14db160303cc43d6b44d9c87cb2eba4a Author: zhangyu117 <[email protected]> AuthorDate: Sat Oct 31 19:58:22 2026 +0800 boards/tricore: fix the TASKING linker scripts 1. triboard_tc4x9_com: use TC1V1.8_DPFPU SmartCode v10.4r1 include.lsl/tc1v1_8.lsl only defines TC1V1.8_DPFPU, TC1V1.8_SPFPU and TC1V1.8_NOFPU, so the board lsl fails to link: ltc E821: parent architecture TC1V1.8 not found Use TC1V1.8_DPFPU for the tc and vtc cores, as tc4dx.lsl does, which matches the --fp-model and c_fpu/fp_fpu libraries used by the build. 2. triboard_tc4x9_com: define the CSA and istack end symbols tricore_internal.h uses __ISTACK0_END as the bottom of the interrupt stack and the iLLD startup code initializes the CSA list from __CSA0/__CSA0_END. The TASKING script defines LCF_CSA_SIZE and LCF_CSA_OFFSET but no CSA section and no __ISTACK0_END: ltc E106: unresolved external: __ISTACK0_END - (tricore_irq.c.o) ltc E106: unresolved external: __CSA0 - (Ifx_Ssw_Tc0.c.o) ltc E106: unresolved external: __CSA0_END - (Ifx_Ssw_Tc0.c.o) Reserve the CSA area at LCF_CSA_OFFSET and alias __ISTACK0_END to the start of the istack group, which gives the same layout as the GNU script. 3. a2g-tc397-5v-tft: handle the empty kernel DLMU The kernel DLMU size is 0, which ltc rejects: ltc E821: memory cpu_dlmu has zero size Place .data/.bss/lmubss in dsram as the GNU script does, drop the unused DLMU heap2, and define __ISTACK0_END used by tricore_internal.h. Signed-off-by: zhangyu117 <[email protected]> --- .../scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel | 24 ++++------------------ .../scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel | 14 +++++++++++-- .../scripts/Lcf_Tasking_Tricore_Tc.lsl.user | 4 ++-- 3 files changed, 18 insertions(+), 24 deletions(-) diff --git a/boards/tricore/tc3xx/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel b/boards/tricore/tc3xx/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel index 7063fb0c74f..652e0b47a38 100644 --- a/boards/tricore/tc3xx/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel +++ b/boards/tricore/tc3xx/a2g-tc397-5v-tft/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel @@ -150,15 +150,6 @@ derivative tc39 map (dest=bus:sri, dest_offset=0xae400000, reserved, size=80K); } - memory cpu_dlmu - { - mau = 8; - size = LCF_DLMU_KERNEL_SIZE; - type = ram; - map cached (dest=bus:sri, dest_offset=LCF_DLMU_KERNEL_START, size=LCF_DLMU_KERNEL_SIZE); - map not_cached (dest=bus:sri, dest_offset=NC_START(LCF_DLMU_KERNEL_START), reserved, size=LCF_DLMU_KERNEL_SIZE); - } - memory kstack { mau = 8; @@ -256,6 +247,7 @@ derivative tc39 "__ISTACK3":="__ISTACK"; "__ISTACK4":="__ISTACK"; "__ISTACK5":="__ISTACK"; + "__ISTACK0_END"="_lc_gb_istack"; group csa_tc(align = 64, attributes=rw, run_addr=mem:dsram[LCF_CSA_OFFSET]) { @@ -402,7 +394,7 @@ derivative tc39 /*Near Absolute Data, selectable with patterns and user defined sections*/ group { - group (ordered, attributes=rw, run_addr = mem:cpu_dlmu) + group (ordered, attributes=rw, run_addr = mem:dsram) { select "(.zdata.zlmudata|.zdata.zlmudata.*)"; select "(.zbss.zlmubss|.zbss.zlmubss.*)"; @@ -543,13 +535,13 @@ derivative tc39 } /*LMU Data sections*/ - group uncached_data(ordered, contiguous, align = 4, attributes=rw, run_addr = mem:cpu_dlmu/not_cached) + group uncached_data(ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram) { select "(.data.uncached.*)"; select "(.bss.uncached.*)"; } - group (ordered, contiguous, align = 4, attributes=rw, run_addr=mem:cpu_dlmu) + group (ordered, contiguous, align = 4, attributes=rw, run_addr=mem:dsram) { group lmubss(attributes=rw, nocopy) { @@ -561,14 +553,6 @@ derivative tc39 select "(.data|.data.*)"; select "(.bss|.bss.*)"; } - - /*Heap2 allocation*/ - group heap2(attributes=rw) - { - heap "heap2" (size = LCF_HEAP_SIZE); - } - "__DLMUHEAP":="_lc_ge_data"; - "__DLMUHEAP_END":=LCF_DLMU_KERNEL_START + LCF_DLMU_KERNEL_SIZE; } /*Far Const Sections, selectable with patterns and user defined sections*/ diff --git a/boards/tricore/tc4xx/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel b/boards/tricore/tc4xx/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel index e9a6535ac89..eb384fad334 100644 --- a/boards/tricore/tc4xx/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel +++ b/boards/tricore/tc4xx/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.kernel @@ -104,14 +104,14 @@ derivative tc4D { core tc { - architecture = TC1V1.8; + architecture = TC1V1.8_DPFPU; space_id_offset = 100; // add 100 to all space IDs in the architecture definition copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections } core vtc { - architecture = TC1V1.8; + architecture = TC1V1.8_DPFPU; import tc; // add all address spaces of core tc to core vtc for linking and locating } @@ -266,12 +266,22 @@ derivative tc4D } "__ISTACK"= sizeof(group:istack) > 0 ? "_lc_ue_istack_tc" : 0; "__ISTACK_END"="_lc_gb_istack"; + "__ISTACK0_END"="_lc_gb_istack"; "__ISTACK0":="__ISTACK"; "__ISTACK1":="__ISTACK"; "__ISTACK2":="__ISTACK"; "__ISTACK3":="__ISTACK"; "__ISTACK4":="__ISTACK"; "__ISTACK5":="__ISTACK"; + + group csa_tc(align = 64, attributes=rw, run_addr=mem:dsram[LCF_CSA_OFFSET]) + { + reserved "csa_tc" (size = LCF_CSA_SIZE); + } + "__CSA"= "_lc_ub_csa_tc"; + "__CSA_END"= "_lc_ue_csa_tc"; + "__CSA0":= "__CSA"; + "__CSA0_END":= "__CSA_END"; } /*Fixed memory Allocations for _START*/ diff --git a/boards/tricore/tc4xx/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user b/boards/tricore/tc4xx/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user index 969d8e055d4..178dc8cc558 100644 --- a/boards/tricore/tc4xx/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user +++ b/boards/tricore/tc4xx/triboard_tc4x9_com/scripts/Lcf_Tasking_Tricore_Tc.lsl.user @@ -44,14 +44,14 @@ derivative tc4D { core tc { - architecture = TC1V1.8; + architecture = TC1V1.8_DPFPU; space_id_offset = 100; // add 100 to all space IDs in the architecture definition copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections } core vtc { - architecture = TC1V1.8; + architecture = TC1V1.8_DPFPU; import tc; // add all address spaces of core tc to core vtc for linking and locating }
