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commit d26b697330dbf16ad06b17deb96b94c2905eec93 Author: Vignesh Pandian <[email protected]> AuthorDate: Mon Nov 2 13:10:12 2026 +0530 arch/arm/mcx-nxxx: Mask glitch detectors before voltage scaling On MCXN236 Rev C silicon, the analog and digital glitch detectors (aGDET and dGDET) are enabled by default and connected to the CHIP_RESET signal through ITRC Output 4. During PLL0 and core voltage scaling, temporary voltage drops can trigger these detectors, causing the chip to reset repeatedly before the scheduler starts. This change masks the glitch detector inputs in ITRC, disables aGDET in SPC, and gates the dGDET clocks in GDET0 and GDET1 during chip initialization. The changes follow the initialization sequence used by the NXP MCUXpresso SDK and prevent unwanted resets during voltage scaling. Signed-off-by: Vignesh Pandian <[email protected]> --- arch/arm/src/mcx-nxxx/hardware/nxxx_gdet.h | 54 +++++++++++++++++++++++++ arch/arm/src/mcx-nxxx/hardware/nxxx_itrc.h | 64 ++++++++++++++++++++++++++++++ arch/arm/src/mcx-nxxx/nxxx_clockconfig.c | 41 +++++++++++++++++++ 3 files changed, 159 insertions(+) diff --git a/arch/arm/src/mcx-nxxx/hardware/nxxx_gdet.h b/arch/arm/src/mcx-nxxx/hardware/nxxx_gdet.h new file mode 100644 index 00000000000..a790d921ca8 --- /dev/null +++ b/arch/arm/src/mcx-nxxx/hardware/nxxx_gdet.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/mcx-nxxx/hardware/nxxx_gdet.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MCX_NXXX_HARDWARE_NXXX_GDET_H +#define __ARCH_ARM_SRC_MCX_NXXX_HARDWARE_NXXX_GDET_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/nxxx_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define NXXX_GDET_ENABLE1_OFFSET 0x0008 + +/* Register Addresses *******************************************************/ + +#define NXXX_GDET0_ENABLE1 (NXXX_GDET0_BASE + NXXX_GDET_ENABLE1_OFFSET) +#define NXXX_GDET1_ENABLE1 (NXXX_GDET1_BASE + NXXX_GDET_ENABLE1_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* GDET_ENABLE1 - GDET Enable Register */ + +#define GDET_ENABLE1_REN1_SHIFT (0) +#define GDET_ENABLE1_REN1_MASK (0x1u << GDET_ENABLE1_REN1_SHIFT) +#define GDET_ENABLE1_REN1(x) (((x) << GDET_ENABLE1_REN1_SHIFT) & \ + GDET_ENABLE1_REN1_MASK) + +#endif /* __ARCH_ARM_SRC_MCX_NXXX_HARDWARE_NXXX_GDET_H */ diff --git a/arch/arm/src/mcx-nxxx/hardware/nxxx_itrc.h b/arch/arm/src/mcx-nxxx/hardware/nxxx_itrc.h new file mode 100644 index 00000000000..f16601b9ad6 --- /dev/null +++ b/arch/arm/src/mcx-nxxx/hardware/nxxx_itrc.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/arm/src/mcx-nxxx/hardware/nxxx_itrc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MCX_NXXX_HARDWARE_NXXX_ITRC_H +#define __ARCH_ARM_SRC_MCX_NXXX_HARDWARE_NXXX_ITRC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/nxxx_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define NXXX_ITRC_OUT4_SEL0_OFFSET 0x0028 +#define NXXX_ITRC_OUT4_SEL1_OFFSET 0x002c + +/* Register Addresses *******************************************************/ + +#define NXXX_ITRC_OUT4_SEL0 (NXXX_ITRC0_BASE + NXXX_ITRC_OUT4_SEL0_OFFSET) +#define NXXX_ITRC_OUT4_SEL1 (NXXX_ITRC0_BASE + NXXX_ITRC_OUT4_SEL1_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* OUT_SEL IN0_SELn - digital glitch detector (dGDET), bits [1:0] */ + +#define ITRC_OUT_SEL_IN0_SELN_SHIFT (0) +#define ITRC_OUT_SEL_IN0_SELN_MASK (0x3u << ITRC_OUT_SEL_IN0_SELN_SHIFT) +#define ITRC_OUT_SEL_IN0_SELN(x) (((x) << ITRC_OUT_SEL_IN0_SELN_SHIFT) & \ + ITRC_OUT_SEL_IN0_SELN_MASK) +#define ITRC_OUT_SEL_IN0_SELN_NONE ITRC_OUT_SEL_IN0_SELN(0x2) + +/* OUT_SEL IN9_SELn - analog glitch detector (aGDET), bits [19:18] */ + +#define ITRC_OUT_SEL_IN9_SELN_SHIFT (18) +#define ITRC_OUT_SEL_IN9_SELN_MASK (0x3u << ITRC_OUT_SEL_IN9_SELN_SHIFT) +#define ITRC_OUT_SEL_IN9_SELN(x) (((x) << ITRC_OUT_SEL_IN9_SELN_SHIFT) & \ + ITRC_OUT_SEL_IN9_SELN_MASK) +#define ITRC_OUT_SEL_IN9_SELN_NONE ITRC_OUT_SEL_IN9_SELN(0x2) + +#endif /* __ARCH_ARM_SRC_MCX_NXXX_HARDWARE_NXXX_ITRC_H */ diff --git a/arch/arm/src/mcx-nxxx/nxxx_clockconfig.c b/arch/arm/src/mcx-nxxx/nxxx_clockconfig.c index 568a7ca5ee2..57f2905bfae 100644 --- a/arch/arm/src/mcx-nxxx/nxxx_clockconfig.c +++ b/arch/arm/src/mcx-nxxx/nxxx_clockconfig.c @@ -42,6 +42,11 @@ #include "hardware/nxxx_scg.h" #include "hardware/nxxx_spc.h" +#ifdef CONFIG_ARCH_CHIP_N236 +# include "hardware/nxxx_itrc.h" +# include "hardware/nxxx_gdet.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -95,6 +100,42 @@ int nxxx_sysinit(void) modifyreg32(SYSCON_LPCAC_CTRL, SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK, 0); +#ifdef CONFIG_ARCH_CHIP_N236 + /* Disable aGDET routing to CHIP_RESET in ITRC */ + + modifyreg32(NXXX_ITRC_OUT4_SEL0, + ITRC_OUT_SEL_IN9_SELN_MASK, + ITRC_OUT_SEL_IN9_SELN_NONE); + modifyreg32(NXXX_ITRC_OUT4_SEL1, + ITRC_OUT_SEL_IN9_SELN_MASK, + ITRC_OUT_SEL_IN9_SELN_NONE); + + /* Disable aGDET interrupt and reset in SPC */ + + modifyreg32(NXXX_SPC_ACTIVE_CFG, 0, + SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK); + modifyreg32(NXXX_SPC_GLITCH_DETECT_SC, + SPC_GLITCH_DETECT_SC_LOCK_MASK, 0); + putreg32(SPC_GLITCH_DETECT_SC_TIMEOUT_MASK, + NXXX_SPC_GLITCH_DETECT_SC); + modifyreg32(NXXX_SPC_GLITCH_DETECT_SC, 0, + SPC_GLITCH_DETECT_SC_LOCK_MASK); + + /* Disable dGDET routing to CHIP_RESET in ITRC */ + + modifyreg32(NXXX_ITRC_OUT4_SEL0, + ITRC_OUT_SEL_IN0_SELN_MASK, + ITRC_OUT_SEL_IN0_SELN_NONE); + modifyreg32(NXXX_ITRC_OUT4_SEL1, + ITRC_OUT_SEL_IN0_SELN_MASK, + ITRC_OUT_SEL_IN0_SELN_NONE); + + /* Disable dGDET reference clocks */ + + putreg32(0, NXXX_GDET0_ENABLE1); + putreg32(0, NXXX_GDET1_ENABLE1); +#endif /* CONFIG_ARCH_CHIP_N236 */ + return OK; }
