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commit 80868c763b5256741efd2689bbb7993512fa3c59 Author: raiden00pl <[email protected]> AuthorDate: Fri Oct 30 13:31:53 2026 +0100 arch/arm/src/stm32n6: Keep the LPTIM clocks running in WFI. The LPTIM LPEN bits reset to 0, so the LPTIMs stopped counting when the idle loop entered WFI. Set them like the TIM and USART1 bits. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h | 15 +++++++++++++++ arch/arm/src/stm32n6/stm32_start.c | 4 ++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h b/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h index 4f3ebaa0f5f..1d6955ac58e 100644 --- a/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h +++ b/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h @@ -69,6 +69,7 @@ #define STM32_RCC_MEMLPENR_OFFSET 0x028c /* SRAM clocks enable in Sleep mode */ #define STM32_RCC_APB1LLPENR_OFFSET 0x02a4 /* APB1 LP clock enable register 1 */ #define STM32_RCC_APB2LPENR_OFFSET 0x02ac /* APB2 LP clock enable register */ +#define STM32_RCC_APB4LLPENR_OFFSET 0x02b4 /* APB4 LP clock enable register 1 */ #define STM32_RCC_DIVENR_OFFSET 0x0240 /* IC divider enable register */ #define STM32_RCC_DIVENSR_OFFSET 0x0a40 /* IC divider enable set register */ @@ -82,6 +83,7 @@ #define STM32_RCC_MEMLPENSR_OFFSET 0x0a8c /* SRAM LP clock enable set register */ #define STM32_RCC_APB1LLPENSR_OFFSET 0x0aa4 /* APB1 LP clock enable set register 1 */ #define STM32_RCC_APB2LPENSR_OFFSET 0x0aac /* APB2 LP clock enable set register */ +#define STM32_RCC_APB4LLPENSR_OFFSET 0x0ab4 /* APB4 LP clock enable set register 1 */ #define STM32_RCC_CCR_OFFSET 0x1000 /* Clock control clear register */ #define STM32_RCC_APB2ENCR_OFFSET 0x126c /* APB2 clock enable clear register */ @@ -119,6 +121,7 @@ #define STM32_RCC_MEMLPENR (STM32_RCC_BASE + STM32_RCC_MEMLPENR_OFFSET) #define STM32_RCC_APB1LLPENR (STM32_RCC_BASE + STM32_RCC_APB1LLPENR_OFFSET) #define STM32_RCC_APB2LPENR (STM32_RCC_BASE + STM32_RCC_APB2LPENR_OFFSET) +#define STM32_RCC_APB4LLPENR (STM32_RCC_BASE + STM32_RCC_APB4LLPENR_OFFSET) #define STM32_RCC_MEMENSR (STM32_RCC_BASE + STM32_RCC_MEMENSR_OFFSET) #define STM32_RCC_AHB4ENSR (STM32_RCC_BASE + STM32_RCC_AHB4ENSR_OFFSET) @@ -129,6 +132,7 @@ #define STM32_RCC_MEMLPENSR (STM32_RCC_BASE + STM32_RCC_MEMLPENSR_OFFSET) #define STM32_RCC_APB1LLPENSR (STM32_RCC_BASE + STM32_RCC_APB1LLPENSR_OFFSET) #define STM32_RCC_APB2LPENSR (STM32_RCC_BASE + STM32_RCC_APB2LPENSR_OFFSET) +#define STM32_RCC_APB4LLPENSR (STM32_RCC_BASE + STM32_RCC_APB4LLPENSR_OFFSET) #define STM32_RCC_CCR (STM32_RCC_BASE + STM32_RCC_CCR_OFFSET) #define STM32_RCC_APB2ENCR (STM32_RCC_BASE + STM32_RCC_APB2ENCR_OFFSET) @@ -344,6 +348,7 @@ #define RCC_APB1LLPENR_TIM11LPEN (1 << 13) /* Bit 13: TIM11 enable in CSLEEP */ #define RCC_APB1LLPENR_TIM10LPEN (1 << 12) /* Bit 12: TIM10 enable in CSLEEP */ +#define RCC_APB1LLPENR_LPTIM1LPEN (1 << 9) /* Bit 9: LPTIM1 enable in CSLEEP */ #define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM14 enable in CSLEEP */ #define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM13 enable in CSLEEP */ #define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM12 enable in CSLEEP */ @@ -377,6 +382,16 @@ RCC_APB2LPENR_TIM16LPEN | RCC_APB2LPENR_TIM17LPEN | \ RCC_APB2LPENR_TIM18LPEN) +/* APB4 peripheral clock enable in Sleep mode (register 1) */ + +#define RCC_APB4LLPENR_LPTIM5LPEN (1 << 12) /* Bit 12: LPTIM5 enable in CSLEEP */ +#define RCC_APB4LLPENR_LPTIM4LPEN (1 << 11) /* Bit 11: LPTIM4 enable in CSLEEP */ +#define RCC_APB4LLPENR_LPTIM3LPEN (1 << 10) /* Bit 10: LPTIM3 enable in CSLEEP */ +#define RCC_APB4LLPENR_LPTIM2LPEN (1 << 9) /* Bit 9: LPTIM2 enable in CSLEEP */ + +#define RCC_APB4LLPENR_ALLLPTIM (RCC_APB4LLPENR_LPTIM2LPEN | RCC_APB4LLPENR_LPTIM3LPEN | \ + RCC_APB4LLPENR_LPTIM4LPEN | RCC_APB4LLPENR_LPTIM5LPEN) + /* Peripheral kernel clock select register 13 */ #define RCC_CCIPR13_USART1SEL_SHIFT (0) diff --git a/arch/arm/src/stm32n6/stm32_start.c b/arch/arm/src/stm32n6/stm32_start.c index a5c2029652c..99590699036 100644 --- a/arch/arm/src/stm32n6/stm32_start.c +++ b/arch/arm/src/stm32n6/stm32_start.c @@ -230,6 +230,10 @@ void __start_c(void) putreg32(RCC_APB1LLPENR_ALLTIM, STM32_RCC_APB1LLPENSR); putreg32(RCC_APB2LPENR_ALLTIM, STM32_RCC_APB2LPENSR); #endif +#ifdef CONFIG_STM32_LPTIM + putreg32(RCC_APB1LLPENR_LPTIM1LPEN, STM32_RCC_APB1LLPENSR); + putreg32(RCC_APB4LLPENR_ALLLPTIM, STM32_RCC_APB4LLPENSR); +#endif /* Mark the board's I/O voltage domains as supply-valid before any GPIO * pad is driven. The mask of PWR_SVMCR3_* bits is board-specific and
