casaroli opened a new pull request, #21430: URL: https://github.com/apache/nuttx/pull/21430
## Summary Three arm chips have ARCH_HAVE_PERF_EVENTS but never call up_perf_init(): mps (mps2-an500, mps2-an521, mps3-an547), rp23xx and fvp-v8r-aarch32. So the cycle counter does not run and its rate stays ULONG_MAX. With ARCH_PERF_EVENTS (the default with SCHED_CRITMONITOR, SCHED_IRQMONITOR, RPMSG_PING and SEGGER_SYSVIEW), every perf time (critmon, irq monitor, sched notes, CPU-time clocks) is then 0. This PR calls up_perf_init() where the other chips of the same arch do it, with the clock of the counter (one commit for each chip): - mps: in __start(), with the processor clock MPS_SYSTICK_CLOCK (the DWT counts processor cycles), as the other Cortex-M chips do. - rp23xx: in __start() with BOARD_SYS_FREQ, and in core1_boot() too, because the DWT is a register of each core. - fvp-v8r-aarch32: at the end of arm_boot() with CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, as the AArch64 fvp-v8r board does. ## Impact Only these chips with ARCH_PERF_EVENTS. Their perf times now come from a running counter. No API change, no documentation change. ## Testing Builds with -Werror, SCHED_CRITMONITOR and ARCH_PERF_EVENTS: | config | mode | result | |---|---|---| | mps2-an500:nsh | flat | OK | | mps2-an500:knsh | protected | OK | | mps2-an521:nsh | flat, Armv8-M | OK | | mps3-an547:nsh | flat, Armv8.1-M | OK | | raspberrypi-pico-2:nsh | flat | OK | | raspberrypi-pico-2:smp | flat, SMP (2 cores) | OK | | fvp-armv8r-aarch32:nsh | flat | OK | Run: mps2-an500:nsh under QEMU boots and runs the test program perfclk.c on master and with this PR. QEMU does not emulate the DWT cycle counter, so perf times stay 0 there in both cases. rp23xx (RP2350) and fvp-v8r-aarch32 (no FVP model here) are build-tested only. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
