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commit e9863f669bd62306ace46b998f4f9544f9dcf8ac Author: raiden00pl <[email protected]> AuthorDate: Fri Oct 30 13:34:10 2026 +0100 arch/arm/src/stm32h7: Enable the WWDG clock on STM32H7R/S. The H7R/S RCC setup never set RCC_APB1ENR1.WWDGEN, so the WWDG registers ignored writes and the watchdog never reset the chip. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/src/stm32h7/stm32h7rsxx_rcc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c b/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c index a49b7e5f4c0..9ee4d4c61b1 100644 --- a/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c @@ -305,6 +305,9 @@ static inline void rcc_enableapb1(void) #ifdef CONFIG_STM32_LPTIM1 regval |= RCC_APB1ENR1_LPTIM1EN; #endif +#ifdef CONFIG_STM32_WWDG + regval |= RCC_APB1ENR1_WWDGEN; +#endif #ifdef CONFIG_STM32_SPI2 regval |= RCC_APB1ENR1_SPI2EN; #endif
