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commit ef59b7fbc75920e1dacbce184ef8bee39d8ec734 Author: raiden00pl <[email protected]> AuthorDate: Wed Nov 11 10:14:47 2026 +0100 arch/arm/stm32: Move the STM32H5 I2C driver to common. The driver becomes common/stm32/stm32_i2c_m33m55_v2.c behind STM32_HAVE_IP_I2C_M33M55_V2; it shares hardware/stm32_i2c_v2.h with the M3/M4 v2 driver. The kernel clock frequencies come from board.h. Assisted-by: Claude:claude-fable-5-1 Signed-off-by: raiden00pl <[email protected]> --- Documentation/guides/chip-specific/stm32_ports.rst | 4 +- arch/arm/src/common/stm32/CMakeLists.txt | 4 + arch/arm/src/common/stm32/Kconfig.have | 6 + arch/arm/src/common/stm32/Kconfig.i2c | 88 +----- arch/arm/src/common/stm32/Make.defs | 4 + arch/arm/src/common/stm32/hardware/stm32_i2c.h | 12 +- arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h | 1 + arch/arm/src/common/stm32/stm32_i2c_clk.h | 121 ++++++++ .../stm32/stm32_i2c_m33m55_v2.c} | 303 +++++++-------------- arch/arm/src/stm32h5/CMakeLists.txt | 4 - arch/arm/src/stm32h5/Kconfig | 1 + arch/arm/src/stm32h5/Make.defs | 4 - arch/arm/src/stm32h5/hardware/stm32_i2c.h | 42 --- arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h | 252 ----------------- arch/arm/src/stm32h5/stm32_i2c.h | 91 ------- arch/arm/src/stm32h5/stm32h5xx_rcc.c | 36 +++ 16 files changed, 282 insertions(+), 691 deletions(-) diff --git a/Documentation/guides/chip-specific/stm32_ports.rst b/Documentation/guides/chip-specific/stm32_ports.rst index 536213afa0a..472a62a4df1 100644 --- a/Documentation/guides/chip-specific/stm32_ports.rst +++ b/Documentation/guides/chip-specific/stm32_ports.rst @@ -616,7 +616,7 @@ EXTI to be done arch/arm/src/stm32h5/stm32_exti_gpio.c FLASH to be done arch/arm/src/stm32h5/stm32_flash.c GPIO to be done arch/arm/src/stm32h5/stm32_gpio.c GPDMA GPDMA arch/arm/src/common/stm32/stm32_dma_gpdma.c -I2C to be done arch/arm/src/stm32h5/stm32_i2c.c +I2C v2 arch/arm/src/common/stm32/stm32_i2c_m33m55_v2.c IWDG v3 arch/arm/src/common/stm32/stm32_iwdg.c ICACHE to be done arch/arm/src/stm32h5/stm32_icache.c OCTOSPI to be done arch/arm/src/stm32h5/stm32_qspi.c @@ -777,7 +777,7 @@ ETH to be done not supported EXTI M33M55 v1 arch/arm/src/common/stm32/stm32_exti_gpio_m33m55_v1.c GPIO M33M55 v1 arch/arm/src/common/stm32/stm32_gpio_m33m55_v1.c GPDMA v1 arch/arm/src/common/stm32/stm32_dma_gpdma.c -I2C to be done not supported +I2C v2 arch/arm/src/common/stm32/stm32_i2c_m33m55_v2.c IWDG v3 arch/arm/src/common/stm32/stm32_iwdg.c LPTIM v2 arch/arm/src/common/stm32/stm32_lptim.c PWR n6 arch/arm/src/stm32n6/stm32_pwr.c diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index e138d877b53..4f2225522df 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -87,6 +87,10 @@ if(CONFIG_STM32_RTC AND CONFIG_STM32_HAVE_IP_RTCC_M33M55_V1) endif() endif() +if(CONFIG_STM32_I2C AND CONFIG_STM32_HAVE_IP_I2C_M33M55_V2) + list(APPEND SRCS stm32_i2c_m33m55_v2.c) +endif() + if(CONFIG_STM32_COMMON_M33) list(APPEND SRCS stm32_allocateheap_m33_v1.c stm32_irq_m33_v1.c stm32_start_m33_v1.c) diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index da048903528..326a6e4d858 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -471,6 +471,12 @@ config STM32_HAVE_IP_I2C_M3M4_V1 config STM32_HAVE_IP_I2C_M3M4_V2 bool +config STM32_HAVE_IP_I2C_M33M55_V2 + bool + ---help--- + I2C v2 of the Cortex-M33 and Cortex-M55 families with the kernel + clock from board.h (STM32H5, STM32N6). + config STM32_HAVE_IP_I2C_M0_V1 bool diff --git a/arch/arm/src/common/stm32/Kconfig.i2c b/arch/arm/src/common/stm32/Kconfig.i2c index cd1832efced..ef52bb29d9e 100644 --- a/arch/arm/src/common/stm32/Kconfig.i2c +++ b/arch/arm/src/common/stm32/Kconfig.i2c @@ -2,94 +2,12 @@ # STM32 I2C configuration options. # -# TODO: generalize H5 specific options ! - config STM32_I2C_SLAVE bool default n -menu "I2C Configuration H5-specific" - depends on STM32_HAVE_I2C_H5 - -menu "Clock Selection" - -choice - depends on STM32_I2C1 - prompt "I2C1 Input Clock Selection" - default STM32_I2C1_CLK_PCLK1 - -config STM32_I2C1_CLK_CSI - bool "CSI" - -config STM32_I2C1_CLK_HSI - bool "HSI" - -config STM32_I2C1_CLK_PCLK1 - bool "PCLK1" - -config STM32_I2C1_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C1 Input Clock Selection - -choice - depends on STM32_I2C2 - prompt "I2C2 Input Clock Selection" - default STM32_I2C2_CLK_PCLK1 - -config STM32_I2C2_CLK_CSI - bool "CSI" - -config STM32_I2C2_CLK_HSI - bool "HSI" - -config STM32_I2C2_CLK_PCLK1 - bool "PCLK1" - -config STM32_I2C2_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C2 Input Clock Selection - -choice - depends on STM32_I2C3 - prompt "I2C3 Input Clock Selection" - default STM32_I2C3_CLK_PCLK3 - -config STM32_I2C3_CLK_CSI - bool "CSI" - -config STM32_I2C3_CLK_HSI - bool "HSI" - -config STM32_I2C3_CLK_PCLK3 - bool "PCLK3" - -config STM32_I2C3_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C3 Input Clock Selection - -choice - depends on STM32_I2C4 - prompt "I2C4 Input Clock Selection" - default STM32_I2C4_CLK_PCLK3 - -config STM32_I2C4_CLK_CSI - bool "CSI" - -config STM32_I2C4_CLK_HSI - bool "HSI" - -config STM32_I2C4_CLK_PCLK3 - bool "PCLK3" - -config STM32_I2C4_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C4 Input Clock Selection - -endmenu # Clock Selection +menu "I2C v2 Configuration" + depends on STM32_HAVE_IP_I2C_M33M55_V2 menu "Rise/Fall Override" @@ -227,7 +145,7 @@ endmenu # Analog Filters endmenu # Filtering -endmenu # "I2C Configuration" +endmenu # I2C v2 Configuration if !STM32_HAVE_I2C_H5 diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index fe74127bfb6..a555c3bb226 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -98,6 +98,10 @@ CHIP_CSRCS += stm32_rtc_m3m4_v1_lowerhalf.c endif endif +ifeq ($(CONFIG_STM32_I2C)$(CONFIG_STM32_HAVE_IP_I2C_M33M55_V2),yy) +CHIP_CSRCS += stm32_i2c_m33m55_v2.c +endif + ifeq ($(CONFIG_STM32_COMMON_M33),y) CHIP_CSRCS += stm32_allocateheap_m33_v1.c CHIP_CSRCS += stm32_irq_m33_v1.c diff --git a/arch/arm/src/common/stm32/hardware/stm32_i2c.h b/arch/arm/src/common/stm32/hardware/stm32_i2c.h index 879ec20a764..19eca23a721 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_i2c.h +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c.h @@ -29,17 +29,23 @@ #if (defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1) + \ defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) + \ - defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)) > 1 + defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) + \ + defined(CONFIG_STM32_HAVE_IP_I2C_M33M55_V2)) > 1 # error Only one STM32 I2C IP version must be selected #endif #if defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1) # include "hardware/stm32_i2c_v2_m0.h" -#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_I2C_M33M55_V2) + +/* The M3M4 and M33M55 drivers of the I2C v2 share its register map */ #if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) # include "stm32_i2c_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_I2C_M33M55_V2) # include "stm32_i2c_v2.h" #else # error STM32 I2C IP version not specified diff --git a/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h index 5f3212b26c3..3b46afa7e68 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h @@ -116,6 +116,7 @@ #define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */ #define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */ #define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */ +#define I2C_CR1_FMP (1 << 24) /* Bit 24: Fast-mode Plus enable */ /* Control register 2 */ diff --git a/arch/arm/src/common/stm32/stm32_i2c_clk.h b/arch/arm/src/common/stm32/stm32_i2c_clk.h new file mode 100644 index 00000000000..0561b029f04 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_i2c_clk.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_i2c_clk.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_CLK_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_CLK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Map each I2C instance to its RCC enable and reset register and bit. The + * bus differs between families: I2C1/2 sit on APB1 everywhere, I2C3 on + * APB1 (H7, N6) or APB3 (H5), I2C4 on APB4 (H7, N6) or APB3 (H5). + */ + +#if defined(RCC_APB1LENR_I2C1EN) +# define STM32_RCC_I2C1_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_I2C1_EN RCC_APB1LENR_I2C1EN +# define STM32_RCC_I2C1_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_I2C1_RST RCC_APB1LRSTR_I2C1RST +#elif defined(RCC_APB1ENR1_I2C1EN) +# define STM32_RCC_I2C1_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_I2C1_EN RCC_APB1ENR1_I2C1EN +# define STM32_RCC_I2C1_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_I2C1_RST RCC_APB1RSTR1_I2C1RST +#elif defined(RCC_APB1ENR_I2C1EN) +# define STM32_RCC_I2C1_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_I2C1_EN RCC_APB1ENR_I2C1EN +# define STM32_RCC_I2C1_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_I2C1_RST RCC_APB1RSTR_I2C1RST +#endif + +#if defined(RCC_APB1LENR_I2C2EN) +# define STM32_RCC_I2C2_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_I2C2_EN RCC_APB1LENR_I2C2EN +# define STM32_RCC_I2C2_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_I2C2_RST RCC_APB1LRSTR_I2C2RST +#elif defined(RCC_APB1ENR1_I2C2EN) +# define STM32_RCC_I2C2_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_I2C2_EN RCC_APB1ENR1_I2C2EN +# define STM32_RCC_I2C2_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_I2C2_RST RCC_APB1RSTR1_I2C2RST +#elif defined(RCC_APB1ENR_I2C2EN) +# define STM32_RCC_I2C2_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_I2C2_EN RCC_APB1ENR_I2C2EN +# define STM32_RCC_I2C2_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_I2C2_RST RCC_APB1RSTR_I2C2RST +#endif + +#if defined(RCC_APB1LENR_I2C3EN) +# define STM32_RCC_I2C3_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_I2C3_EN RCC_APB1LENR_I2C3EN +# define STM32_RCC_I2C3_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_I2C3_RST RCC_APB1LRSTR_I2C3RST +#elif defined(RCC_APB3ENR_I2C3EN) +# define STM32_RCC_I2C3_EN_REG STM32_RCC_APB3ENR +# define STM32_RCC_I2C3_EN RCC_APB3ENR_I2C3EN +# define STM32_RCC_I2C3_RST_REG STM32_RCC_APB3RSTR +# define STM32_RCC_I2C3_RST RCC_APB3RSTR_I2C3RST +#elif defined(RCC_APB1ENR1_I2C3EN) +# define STM32_RCC_I2C3_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_I2C3_EN RCC_APB1ENR1_I2C3EN +# define STM32_RCC_I2C3_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_I2C3_RST RCC_APB1RSTR1_I2C3RST +#elif defined(RCC_APB1ENR_I2C3EN) +# define STM32_RCC_I2C3_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_I2C3_EN RCC_APB1ENR_I2C3EN +# define STM32_RCC_I2C3_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_I2C3_RST RCC_APB1RSTR_I2C3RST +#endif + +#if defined(RCC_APB4LENR_I2C4EN) +# define STM32_RCC_I2C4_EN_REG STM32_RCC_APB4LENR +# define STM32_RCC_I2C4_EN RCC_APB4LENR_I2C4EN +# define STM32_RCC_I2C4_RST_REG STM32_RCC_APB4LRSTR +# define STM32_RCC_I2C4_RST RCC_APB4LRSTR_I2C4RST +#elif defined(RCC_APB3ENR_I2C4EN) +# define STM32_RCC_I2C4_EN_REG STM32_RCC_APB3ENR +# define STM32_RCC_I2C4_EN RCC_APB3ENR_I2C4EN +# define STM32_RCC_I2C4_RST_REG STM32_RCC_APB3RSTR +# define STM32_RCC_I2C4_RST RCC_APB3RSTR_I2C4RST +#elif defined(RCC_APB4ENR_I2C4EN) +# define STM32_RCC_I2C4_EN_REG STM32_RCC_APB4ENR +# define STM32_RCC_I2C4_EN RCC_APB4ENR_I2C4EN +# define STM32_RCC_I2C4_RST_REG STM32_RCC_APB4RSTR +# define STM32_RCC_I2C4_RST RCC_APB4RSTR_I2C4RST +#elif defined(RCC_APB1ENR1_I2C4EN) +# define STM32_RCC_I2C4_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_I2C4_EN RCC_APB1ENR1_I2C4EN +# define STM32_RCC_I2C4_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_I2C4_RST RCC_APB1RSTR1_I2C4RST +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_CLK_H */ diff --git a/arch/arm/src/stm32h5/stm32_i2c.c b/arch/arm/src/common/stm32/stm32_i2c_m33m55_v2.c similarity index 92% rename from arch/arm/src/stm32h5/stm32_i2c.c rename to arch/arm/src/common/stm32/stm32_i2c_m33m55_v2.c index 7a12a60a683..f77cce4db4a 100644 --- a/arch/arm/src/stm32h5/stm32_i2c.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m33m55_v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h5/stm32_i2c.c + * arch/arm/src/common/stm32/stm32_i2c_m33m55_v2.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2024 Kyle Wilson. All rights reserved. @@ -46,15 +46,16 @@ /* -------------------------------------------------------------------------- * - * STM32 H5 I2C Driver + * STM32 I2C v2 Driver for the Cortex-M33 and Cortex-M55 families with a + * per-instance I2C kernel clock (STM32H5, STM32N6). * * Supports: * - Master operation: * Standard-mode (up to 100 kHz) * Fast-mode (up to 400 kHz) * Fast-mode Plus (up to 1 MHz) - * fI2CCLK clock source selection is based on - * STM32_RCC_CCIPR4_I2CxSRC + * The I2C kernel clock frequency comes from STM32_I2Cn_FREQUENCY in + * board.h * * - Multiple instances (shared bus) * - Interrupt based operation @@ -154,13 +155,9 @@ * * Configuration: * - * To use this driver, enable the following configuration variable: - * - * One of: - * - * CONFIG_STM32_STM32H5XXXXX - * - * and one or more interfaces: + * To use this driver, the chip must select + * CONFIG_STM32_HAVE_IP_I2C_M33M55_V2 and the configuration must enable one + * or more interfaces: * * CONFIG_STM32_I2C1 * CONFIG_STM32_I2C2 @@ -220,10 +217,9 @@ #include <arch/board/board.h> #include "arm_internal.h" -#include "stm32_rcc.h" +#include "stm32.h" #include "stm32_i2c.h" -#include "stm32_gpio.h" -#include "hardware/stm32_pinmap.h" +#include "stm32_i2c_clk.h" /* At least one I2C peripheral must be enabled */ @@ -364,6 +360,21 @@ struct stm32_trace_s clock_t time; /* First of event or first status */ }; +/* The I2C kernel clock frequency comes from board.h */ + +#if defined(CONFIG_STM32_I2C1) && !defined(STM32_I2C1_FREQUENCY) +# error "STM32_I2C1_FREQUENCY must be defined in board.h" +#endif +#if defined(CONFIG_STM32_I2C2) && !defined(STM32_I2C2_FREQUENCY) +# error "STM32_I2C2_FREQUENCY must be defined in board.h" +#endif +#if defined(CONFIG_STM32_I2C3) && !defined(STM32_I2C3_FREQUENCY) +# error "STM32_I2C3_FREQUENCY must be defined in board.h" +#endif +#if defined(CONFIG_STM32_I2C4) && !defined(STM32_I2C4_FREQUENCY) +# error "STM32_I2C4_FREQUENCY must be defined in board.h" +#endif + /* I2C Device hardware configuration */ struct stm32_i2c_config_s @@ -489,10 +500,10 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, - .clk_reg = STM32_RCC_APB1LENR, - .clk_bit = RCC_APB1LENR_I2C1EN, - .reset_reg = STM32_RCC_APB1LRSTR, - .reset_bit = RCC_APB1LRSTR_I2C1RST, + .clk_reg = STM32_RCC_I2C1_EN_REG, + .clk_bit = STM32_RCC_I2C1_EN, + .reset_reg = STM32_RCC_I2C1_RST_REG, + .reset_bit = STM32_RCC_I2C1_RST, .scl_pin = GPIO_I2C1_SCL, .sda_pin = GPIO_I2C1_SDA, #ifndef CONFIG_I2C_POLLED @@ -527,10 +538,10 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, - .clk_reg = STM32_RCC_APB1LENR, - .clk_bit = RCC_APB1LENR_I2C2EN, - .reset_reg = STM32_RCC_APB1LRSTR, - .reset_bit = RCC_APB1LRSTR_I2C2RST, + .clk_reg = STM32_RCC_I2C2_EN_REG, + .clk_bit = STM32_RCC_I2C2_EN, + .reset_reg = STM32_RCC_I2C2_RST_REG, + .reset_bit = STM32_RCC_I2C2_RST, .scl_pin = GPIO_I2C2_SCL, .sda_pin = GPIO_I2C2_SDA, #ifndef CONFIG_I2C_POLLED @@ -565,10 +576,10 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, - .clk_reg = STM32_RCC_APB3ENR, - .clk_bit = RCC_APB3ENR_I2C3EN, - .reset_reg = STM32_RCC_APB3RSTR, - .reset_bit = RCC_APB3RSTR_I2C3RST, + .clk_reg = STM32_RCC_I2C3_EN_REG, + .clk_bit = STM32_RCC_I2C3_EN, + .reset_reg = STM32_RCC_I2C3_RST_REG, + .reset_bit = STM32_RCC_I2C3_RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, #ifndef CONFIG_I2C_POLLED @@ -603,10 +614,10 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, - .clk_reg = STM32_RCC_APB3ENR, - .clk_bit = RCC_APB3ENR_I2C4EN, - .reset_reg = STM32_RCC_APB3RSTR, - .reset_bit = RCC_APB3RSTR_I2C4RST, + .clk_reg = STM32_RCC_I2C4_EN_REG, + .clk_bit = STM32_RCC_I2C4_EN, + .reset_reg = STM32_RCC_I2C4_RST_REG, + .reset_bit = STM32_RCC_I2C4_RST, .scl_pin = GPIO_I2C4_SCL, .sda_pin = GPIO_I2C4_SDA, #ifndef CONFIG_I2C_POLLED @@ -763,8 +774,8 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #ifndef CONFIG_I2C_POLLED static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) { - stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, - (I2C_CR1_TXRX | I2C_CR1_NACKIE)); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif @@ -1284,87 +1295,55 @@ static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, switch (priv->config->base) { #ifdef CONFIG_STM32_I2C1 - case STM32_I2C1_BASE: -# if defined(CONFIG_STM32_I2C1_CLK_HSI) - i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32_I2C1_CLK_CSI) - i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32_I2C1_CLK_PCLK1) - i2c_ker_ck = STM32_PCLK1_FREQUENCY; -# else - i2c_ker_ck = STM32_PLL3R_FREQUENCY; -# endif - anfoff = CONFIG_STM32_I2C1_ANFOFF; - dnf = CONFIG_STM32_I2C1_DNF; + case STM32_I2C1_BASE: + i2c_ker_ck = STM32_I2C1_FREQUENCY; + anfoff = CONFIG_STM32_I2C1_ANFOFF; + dnf = CONFIG_STM32_I2C1_DNF; # ifdef CONFIG_STM32_I2C1_RF_OVERRIDE - tr_max = CONFIG_STM32_I2C1_RISE; - tf_max = CONFIG_STM32_I2C1_FALL; - rf_override = true; + tr_max = CONFIG_STM32_I2C1_RISE; + tf_max = CONFIG_STM32_I2C1_FALL; + rf_override = true; # endif - break; + break; #endif #ifdef CONFIG_STM32_I2C2 - case STM32_I2C2_BASE: -# if defined(CONFIG_STM32_I2C2_CLK_HSI) - i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32_I2C2_CLK_CSI) - i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32_I2C2_CLK_PCLK1) - i2c_ker_ck = STM32_PCLK1_FREQUENCY; -# else - i2c_ker_ck = STM32_PLL3R_FREQUENCY; -# endif - anfoff = CONFIG_STM32_I2C2_ANFOFF; - dnf = CONFIG_STM32_I2C2_DNF; + case STM32_I2C2_BASE: + i2c_ker_ck = STM32_I2C2_FREQUENCY; + anfoff = CONFIG_STM32_I2C2_ANFOFF; + dnf = CONFIG_STM32_I2C2_DNF; # ifdef CONFIG_STM32_I2C2_RF_OVERRIDE - tr_max = CONFIG_STM32_I2C2_RISE; - tf_max = CONFIG_STM32_I2C2_FALL; - rf_override = true; + tr_max = CONFIG_STM32_I2C2_RISE; + tf_max = CONFIG_STM32_I2C2_FALL; + rf_override = true; # endif - break; + break; #endif #ifdef CONFIG_STM32_I2C3 - case STM32_I2C3_BASE: -# if defined(CONFIG_STM32_I2C3_CLK_HSI) - i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32_I2C3_CLK_CSI) - i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32_I2C3_CLK_PCLK3) - i2c_ker_ck = STM32_PCLK3_FREQUENCY; -# else - i2c_ker_ck = STM32_PLL3R_FREQUENCY; -# endif - anfoff = CONFIG_STM32_I2C3_ANFOFF; - dnf = CONFIG_STM32_I2C3_DNF; + case STM32_I2C3_BASE: + i2c_ker_ck = STM32_I2C3_FREQUENCY; + anfoff = CONFIG_STM32_I2C3_ANFOFF; + dnf = CONFIG_STM32_I2C3_DNF; # ifdef CONFIG_STM32_I2C3_RF_OVERRIDE - tr_max = CONFIG_STM32_I2C3_RISE; - tf_max = CONFIG_STM32_I2C3_FALL; - rf_override = true; + tr_max = CONFIG_STM32_I2C3_RISE; + tf_max = CONFIG_STM32_I2C3_FALL; + rf_override = true; # endif - break; + break; #endif #ifdef CONFIG_STM32_I2C4 - case STM32_I2C4_BASE: -# if defined(CONFIG_STM32_I2C4_CLK_HSI) - i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32_I2C4_CLK_CSI) - i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32_I2C4_CLK_PCLK3) - i2c_ker_ck = STM32_PCLK3_FREQUENCY; -# else - i2c_ker_ck = STM32_PLL3R_FREQUENCY; -# endif - anfoff = CONFIG_STM32_I2C4_ANFOFF; - dnf = CONFIG_STM32_I2C4_DNF; + case STM32_I2C4_BASE: + i2c_ker_ck = STM32_I2C4_FREQUENCY; + anfoff = CONFIG_STM32_I2C4_ANFOFF; + dnf = CONFIG_STM32_I2C4_DNF; # ifdef CONFIG_STM32_I2C4_RF_OVERRIDE - tr_max = CONFIG_STM32_I2C4_RISE; - tf_max = CONFIG_STM32_I2C4_FALL; - rf_override = true; + tr_max = CONFIG_STM32_I2C4_RISE; + tf_max = CONFIG_STM32_I2C4_FALL; + rf_override = true; # endif - break; + break; #endif - default: - break; + default: + break; } /* Set i2c_ker_ck period ti2cclk in nanoseconds */ @@ -2383,98 +2362,6 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) up_enable_irq(priv->config->er_irq); #endif - /* - Provide means to set peripheral clock source via RCC_CCIPR4_I2CxSEL */ - - switch (priv->config->base) - { -#ifdef CONFIG_STM32_I2C1 - case STM32_I2C1_BASE: -# if defined(CONFIG_STM32_I2C1_CLK_HSI) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C1SEL_MASK, - RCC_CCIPR4_I2C1SEL_HSIKERCK); -# elif defined(CONFIG_STM32_I2C1_CLK_CSI) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C1SEL_MASK, - RCC_CCIPR4_I2C1SEL_CSIKERCK); -# elif defined(CONFIG_STM32_I2C1_CLK_PCLK1) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C1SEL_MASK, - RCC_CCIPR4_I2C1SEL_RCCPCLK1); -# else - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C1SEL_MASK, - RCC_CCIPR4_I2C1SEL_PLL3RCK); -# endif - break; -#endif -#ifdef CONFIG_STM32_I2C2 - case STM32_I2C2_BASE: -# if defined(CONFIG_STM32_I2C2_CLK_HSI) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C2SEL_MASK, - RCC_CCIPR4_I2C2SEL_HSIKERCK); -# elif defined(CONFIG_STM32_I2C2_CLK_CSI) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C2SEL_MASK, - RCC_CCIPR4_I2C2SEL_CSIKERCK); -# elif defined(CONFIG_STM32_I2C2_CLK_PCLK1) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C2SEL_MASK, - RCC_CCIPR4_I2C2SEL_RCCPCLK1); -# else - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C2SEL_MASK, - RCC_CCIPR4_I2C2SEL_PLL3RCK); -# endif - break; -#endif -#ifdef CONFIG_STM32_I2C3 - case STM32_I2C3_BASE: -# if defined(CONFIG_STM32_I2C3_CLK_HSI) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C3SEL_MASK, - RCC_CCIPR4_I2C3SEL_HSIKERCK); -# elif defined(CONFIG_STM32_I2C3_CLK_CSI) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C3SEL_MASK, - RCC_CCIPR4_I2C3SEL_CSIKERCK); -# elif defined(CONFIG_STM32_I2C3_CLK_PCLK3) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C3SEL_MASK, - RCC_CCIPR4_I2C3SEL_RCCPCLK3); -# else - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C3SEL_MASK, - RCC_CCIPR4_I2C3SEL_PLL3RCK); -# endif - break; -#endif -#ifdef CONFIG_STM32_I2C4 - case STM32_I2C4_BASE: -# if defined(CONFIG_STM32_I2C4_CLK_HSI) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C4SEL_MASK, - RCC_CCIPR4_I2C4SEL_HSIKERCK); -# elif defined(CONFIG_STM32_I2C4_CLK_CSI) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C4SEL_MASK, - RCC_CCIPR4_I2C4SEL_CSIKERCK); -# elif defined(CONFIG_STM32_I2C4_CLK_PCLK3) - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C4SEL_MASK, - RCC_CCIPR4_I2C4SEL_RCCPCLK3); -# else - modifyreg32(STM32_RCC_CCIPR4, - RCC_CCIPR4_I2C4SEL_MASK, - RCC_CCIPR4_I2C4SEL_PLL3RCK); -# endif - break; -#endif - default: - break; - } - /* Force a frequency update */ priv->frequency = 0; @@ -2677,7 +2564,7 @@ static int stm32_i2c_process(struct i2c_master_s *dev, } else if (status & I2C_INT_PECERR) { - /* PEC Error in reception (SMBus Only) */ + /* PEC Error in reception (SMBus Only) */ i2cerr("ERROR: I2C PEC Error\n"); errval = EPROTO; @@ -2964,31 +2851,31 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, switch (pmstate) { - case PM_NORMAL: - case PM_IDLE: - break; + case PM_NORMAL: + case PM_IDLE: + break; - case PM_STANDBY: - case PM_SLEEP: + case PM_STANDBY: + case PM_SLEEP: - /* Check if exclusive lock for I2C bus is held. */ + /* Check if exclusive lock for I2C bus is held. */ - if (nxmutex_is_locked(&priv->lock)) - { - /* Exclusive lock is held, do not allow entry to deeper PM - * states. - */ + if (nxmutex_is_locked(&priv->lock)) + { + /* Exclusive lock is held, do not allow entry to deeper PM + * states. + */ - return -EBUSY; - } + return -EBUSY; + } - break; + break; - default: + default: - /* Should not get here */ + /* Should not get here */ - break; + break; } return OK; diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt index 64f67b99363..1c9d5b50f0f 100644 --- a/arch/arm/src/stm32h5/CMakeLists.txt +++ b/arch/arm/src/stm32h5/CMakeLists.txt @@ -36,10 +36,6 @@ endif() list(APPEND SRCS stm32_rcc.c stm32_pwr.c stm32_lse.c stm32_sdmmc.c) -if(CONFIG_STM32_I2C) - list(APPEND SRCS stm32_i2c.c) -endif() - if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) endif() diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index c8c411a8b86..d8fa984e089 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -41,6 +41,7 @@ config STM32_H5_PERIPHERALS select STM32_HAVE_USART_H5 select STM32_HAVE_USART_WUS select STM32_HAVE_I2C_H5 + select STM32_HAVE_IP_I2C_M33M55_V2 select STM32_HAVE_CRC select STM32_HAVE_IP_WDG_V3 diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs index 277bcf66357..b38728796e3 100644 --- a/arch/arm/src/stm32h5/Make.defs +++ b/arch/arm/src/stm32h5/Make.defs @@ -44,10 +44,6 @@ CHIP_CSRCS += stm32_rcc.c CHIP_CSRCS += stm32_pwr.c CHIP_CSRCS += stm32_lse.c stm32_sdmmc.c -ifeq ($(CONFIG_STM32_I2C),y) -CHIP_CSRCS += stm32_i2c.c -endif - ifeq ($(CONFIG_ADC),y) CHIP_CSRCS += stm32_adc.c endif diff --git a/arch/arm/src/stm32h5/hardware/stm32_i2c.h b/arch/arm/src/stm32h5/hardware/stm32_i2c.h deleted file mode 100644 index d0481396153..00000000000 --- a/arch/arm/src/stm32h5/hardware/stm32_i2c.h +++ /dev/null @@ -1,42 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/hardware/stm32_i2c.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_I2C_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> -#include "chip.h" - -#if defined(CONFIG_STM32_STM32H50XXX) || \ - defined(CONFIG_STM32_STM32H52XXX) || \ - defined(CONFIG_STM32_STM32H53XXX) || \ - defined(CONFIG_STM32_STM32H56XXX) || \ - defined(CONFIG_STM32_STM32H57XXX) -# include "hardware/stm32h5xxx_i2c.h" -#else -# error "Unsupported STM32 H5 I2C" -#endif -#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_I2C_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h deleted file mode 100644 index 5b3adf5963e..00000000000 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h +++ /dev/null @@ -1,252 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_I2C_H -#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_I2C_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NI2C > 0 -# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) -# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) -# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) -# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET) -# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET) -# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET) -# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET) -# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET) -# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET) -# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET) -# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) -#endif - -#if STM32_NI2C > 1 -# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) -# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) -# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) -# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET) -# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET) -# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET) -# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET) -# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET) -# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET) -# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET) -# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) -#endif - -#if STM32_NI2C > 2 -# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) -# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) -# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) -# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET) -# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET) -# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET) -# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET) -# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET) -# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET) -# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET) -# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) -#endif - -#if STM32_NI2C > 3 -# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) -# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) -# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) -# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET) -# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET) -# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET) -# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET) -# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET) -# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET) -# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET) -# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */ -#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */ -#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */ -#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */ -#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */ -#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */ -#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */ -#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */ -#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */ -#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT) -# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) -# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ - -#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ -#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ -#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */ -#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */ -#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */ -#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */ -#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */ -#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */ -#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */ -#define I2C_CR1_FMP (1 << 24) /* Bit 24: FMP enable */ - -/* Control register 2 */ - -#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */ -#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT) -#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */ -#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT) -#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */ -#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */ -#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */ -#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */ -#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */ -#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */ -#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */ -#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT) -#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */ -#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */ -#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */ - -/* Own address register 1 */ - -#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */ -#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT) -#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */ -#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT) -#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */ -#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */ - -/* Own address register 2 */ - -#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */ -#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT) -#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */ -#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT) -# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */ -# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */ -# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */ -# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */ -# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */ -# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */ -# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */ -# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */ - -#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */ - -/* Timing register */ - -#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */ -#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT) -# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */ - -#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */ -#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT) -# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */ - -#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */ -#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT) -# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */ - -#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */ -#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT) -# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */ - -#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */ -#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT) -# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */ - -/* Timeout register */ - -#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */ -#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT) -# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT) -#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */ -#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */ -#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT) -# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT) -#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ - -/* Fields unique to the Interrupt and Status register */ - -#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */ -#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */ -#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */ -#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */ -#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */ -#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */ -#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */ -#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */ -#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT) - -/* Interrupt and Status register and interrupt clear register */ - -/* Common interrupt bits */ - -#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ -#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */ -#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */ -#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */ -#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */ -#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */ -#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */ -#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */ -#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */ - -#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT) - -#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \ - | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT) - -/* Packet error checking register */ - -#define I2C_PECR_MASK (0xff) - -/* Receive data register */ - -#define I2C_RXDR_MASK (0xff) - -/* Transmit data register */ - -#define I2C_TXDR_MASK (0xff) - -#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_I2C_H */ diff --git a/arch/arm/src/stm32h5/stm32_i2c.h b/arch/arm/src/stm32h5/stm32_i2c.h deleted file mode 100644 index 87c3f6a1b02..00000000000 --- a/arch/arm/src/stm32h5/stm32_i2c.h +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_i2c.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32H5_STM32_I2C_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> -#include <nuttx/i2c/i2c_master.h> - -#include "chip.h" -#include "hardware/stm32h5xxx_i2c.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If a dynamic timeout is selected, then a non-negative, non-zero micro- - * seconds per byte value must be provided as well. - */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32_I2C_DYNTIMEO -# endif -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_initialize - * - * Description: - * Initialize the selected I2C port. And return a unique instance of struct - * struct i2c_master_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * Port number (for hardware that has multiple I2C interfaces) - * - * Returned Value: - * Valid I2C device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct i2c_master_s *stm32_i2cbus_initialize(int port); - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_i2cbus_initialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); - -#endif /* __ARCH_ARM_SRC_STM32H5_STM32_I2C_H */ diff --git a/arch/arm/src/stm32h5/stm32h5xx_rcc.c b/arch/arm/src/stm32h5/stm32h5xx_rcc.c index 683f1c67477..324fdbba841 100644 --- a/arch/arm/src/stm32h5/stm32h5xx_rcc.c +++ b/arch/arm/src/stm32h5/stm32h5xx_rcc.c @@ -1318,6 +1318,42 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_CCIPR3); #endif + /* Configure I2C1 source clock */ + +#if defined(STM32_RCC_CCIPR4_I2C1SEL) + regval = getreg32(STM32_RCC_CCIPR4); + regval &= ~RCC_CCIPR4_I2C1SEL_MASK; + regval |= STM32_RCC_CCIPR4_I2C1SEL; + putreg32(regval, STM32_RCC_CCIPR4); +#endif + + /* Configure I2C2 source clock */ + +#if defined(STM32_RCC_CCIPR4_I2C2SEL) + regval = getreg32(STM32_RCC_CCIPR4); + regval &= ~RCC_CCIPR4_I2C2SEL_MASK; + regval |= STM32_RCC_CCIPR4_I2C2SEL; + putreg32(regval, STM32_RCC_CCIPR4); +#endif + + /* Configure I2C3 source clock */ + +#if defined(STM32_RCC_CCIPR4_I2C3SEL) + regval = getreg32(STM32_RCC_CCIPR4); + regval &= ~RCC_CCIPR4_I2C3SEL_MASK; + regval |= STM32_RCC_CCIPR4_I2C3SEL; + putreg32(regval, STM32_RCC_CCIPR4); +#endif + + /* Configure I2C4 source clock */ + +#if defined(STM32_RCC_CCIPR4_I2C4SEL) + regval = getreg32(STM32_RCC_CCIPR4); + regval &= ~RCC_CCIPR4_I2C4SEL_MASK; + regval |= STM32_RCC_CCIPR4_I2C4SEL; + putreg32(regval, STM32_RCC_CCIPR4); +#endif + /* Configure USB source clock */ #if defined(STM32_CLKUSB_SEL)
