btashton commented on pull request #2916: URL: https://github.com/apache/incubator-nuttx/pull/2916#issuecomment-785347296
The XIP controller handles this for us on this chip: """ The cache is 16 kB, two way set-associative, 1 cycle hit. It is internal to the XIP subsystem, and only affects accesses to XIP flash, so software does not have to consider cache coherence, unless performing flash programming operations. """ --Brennan On Wed, Feb 24, 2021, 11:58 AM patacongo <notificati...@github.com> wrote: > One thing I was thinking about for SMP on the RP4020 is the caching. I > asked earlier about this and was told that there some kind of caching or > pre-fetch was supported. Then I wondered about how coherency is maintained. > This is a really complex issue on Cortex-A. > > Is there a single pre-fetch cache? Or separate caches for each CPU? If > they are shared then there is no issue. If there are not, then how is > coherency maintained if one CPU modifies data (or instructions) that is in > the the cache of the other? > > — > You are receiving this because you are subscribed to this thread. > Reply to this email directly, view it on GitHub > <https://github.com/apache/incubator-nuttx/pull/2916#issuecomment-785334871>, > or unsubscribe > <https://github.com/notifications/unsubscribe-auth/AABKJPNOX3JIME5IPKZDSWLTAVK6ZANCNFSM4YEY2BVQ> > . > ---------------------------------------------------------------- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. For queries about this service, please contact Infrastructure at: us...@infra.apache.org
