pussuw commented on a change in pull request #5273: URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787576120
########## File path: arch/risc-v/src/common/riscv_mmu.h ########## @@ -0,0 +1,306 @@ +/**************************************************************************** + * arch/risc-v/src/rv64gc/riscv_mmu.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_ +#define ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_ + +#if (__riscv_xlen != 64) +#error "This MMU implementation is for xlen 64" +#endif + +/* RV64 page size */ + +#define RV_MMU_PAGE_SHIFT (12) +#define RV_MMU_PAGE_SIZE (1 << RV_MMU_PAGE_SHIFT) /* 4K pages */ + +/* Amount of page table levels */ + +#define RV_MMU_PT_LEVELS (ARCH_PGT_MAX_LEVELS) + +/* Supervisor Address Translation and Protection (satp) */ + +#define SATP_PPN_SHIFT (0) +#define SATP_PPN_MASK (((1ul << 44) - 1) << SATP_PPN_SHIFT) +#define SATP_ASID_SHIFT (44) +#define SATP_ASID_MASK (((1ul << 16) - 1) << SATP_ASID_SHIFT) +#define SATP_MODE_SHIFT (60) +#define SATP_MODE_MASK (((1ul << 4) - 1) << SATP_MODE_SHIFT) + +/* Modes, 1-7 and 10-15 are reserved */ + +#define SATP_MODE_BARE (0ul) +#define SATP_MODE_SV39 (8ul) +#define SATP_MODE_SV48 (9ul) + +/* satp address to PPN translation */ + +#define SATP_ADDR_TO_PPN(_addr) ((_addr) >> RV_MMU_PAGE_SHIFT) + +/* Common Page Table Entry (PTE) bits */ + +#define PTE_VALID (1 << 0) /* PTE is valid */ +#define PTE_R (1 << 1) /* Page is readable */ +#define PTE_W (1 << 2) /* Page is writable */ +#define PTE_X (1 << 3) /* Page is executable */ +#define PTE_U (1 << 4) /* Page is a user mode page */ +#define PTE_G (1 << 5) /* Page is a global mapping */ +#define PTE_A (1 << 6) /* Page has been accessed */ +#define PTE_D (1 << 7) /* Page is dirty */ + +/* Check if leaf PTE entry or not (if X/W/R are set it is) */ + +#define PTE_LEAF_MASK (7 << 1) + +/* Flags for user page tables */ + +#define MMU_UPGT_FLAGS (0) + +/* Flags for user FLASH (RX) and user RAM (RW) */ + +#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U) +#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U) + +/* SvX definitions, only Sv39 is currently supported, but it should be + * trivial to extend the driver to support other SvX implementations + * + * Sv39 has: + * - 4K page size + * - 3 page table levels + * - 9-bit VPN width + */ + +#ifdef CONFIG_ARCH_MMU_TYPE_SV39 +#define RV_MMU_PTE_PADDR_SHIFT (10) +#define RV_MMU_PTE_PPN_MASK ((1 << RV_MMU_PTE_PADDR_SHIFT) - 1) +#define RV_MMU_PTE_PPN_SHIFT (2) +#define RV_MMU_VPN_WIDTH (9) +#define RV_MMU_VPN_MASK ((1 << RV_MMU_VPN_WIDTH) - 1) +#define RV_MMU_VADDR_SHIFT(_n) (RV_MMU_PAGE_SHIFT + RV_MMU_VPN_WIDTH * \ + (RV_MMU_PT_LEVELS - (_n))) +#define RV_MMU_SATP_MODE (SATP_MODE_SV39) +#define RV_MMU_L1_PAGE_SIZE (0x40000000) /* 1G */ +#define RV_MMU_L2_PAGE_SIZE (0x200000) /* 2M */ +#define RV_MMU_L3_PAGE_SIZE (0x1000) /* 4K */ +#else +#error "Unsupported RISC-V MMU implementation selected" +#endif /* CONFIG_ARCH_MMU_TYPE_SV39 */ + +/**************************************************************************** + * Name: satp_reg + * + * Description: + * Utility function to build satp register value for input parameters + * + * Input Parameters: + * pgbase - The physical base address of the translation table base + * asid - Address space identifier. This can be used to identify different + * address spaces. It is not necessary to use this, nor is it necessary + * for the RISC-V implementation to implement such bits. This means in + * practice that the value should not be used in this generic driver. + * + ****************************************************************************/ + +static inline uint64_t satp_reg(uint64_t pgbase, uint16_t asid) +{ + uint64_t reg; + reg = ((RV_MMU_SATP_MODE << SATP_MODE_SHIFT) & SATP_MODE_MASK); + reg |= (((uint64_t)asid << SATP_ASID_SHIFT) & SATP_ASID_MASK); + reg |= ((SATP_ADDR_TO_PPN(pgbase) << SATP_PPN_SHIFT) & SATP_PPN_MASK); + return reg; +} + +/**************************************************************************** + * Name: mmu_write_satp + * + * Description: + * Write satp + * + * Input Parameters: + * reg - satp value + * + ****************************************************************************/ + +static inline void mmu_write_satp(uint64_t reg) Review comment: Thanks, will re-factor the arguments -- This is an automated message from the Apache Git Service. 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