pkarashchenko commented on a change in pull request #5352: URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793509344
########## File path: arch/xtensa/src/esp32s3/esp32s3_irq.c ########## @@ -0,0 +1,686 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <nuttx/board.h> +#include <arch/irq.h> +#include <arch/board/board.h> + +#include "xtensa.h" + +#include "hardware/esp32s3_soc.h" +#include "hardware/esp32s3_system.h" +#include "hardware/esp32s3_interrupt_core0.h" + +#include "esp32s3_irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ to CPU and CPU interrupts mapping: + * + * Encoding: CIIIIIII + * C: CPU that enabled the interrupt (0 = PRO, 1 = APP). + * I: Associated CPU interrupt. + */ + +#define IRQ_UNMAPPED 0xff +#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07) +#define IRQ_GETCPUINT(m) ((m) & 0x7f) +#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i)) + +/* CPU interrupts to peripheral mapping: + * + * Encoding: EPPPPPPP + * E: CPU interrupt status (0 = Disabled, 1 = Enabled). + * P: Attached peripheral. + */ + +#define CPUINT_UNASSIGNED 0x7f +#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07) +#define CPUINT_GETIRQ(m) ((m) & 0x7f) +#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80) +#define CPUINT_DISABLE(m) ((m) & 0x7f) +#define CPUINT_ENABLE(m) ((m) | 0x80) + +/* Mapping Peripheral IDs to map register addresses. */ + +#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2)) + +/* CPU interrupts can be detached from any peripheral source by setting the + * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29). + */ + +#define NO_CPUINT ESP32S3_CPUINT_TIMER0 + +/* Priority range is 1-5 */ + +#define ESP32S3_MIN_PRIORITY 1 +#define ESP32S3_MAX_PRIORITY 5 +#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a reference to the current interrupt level + * register storage structure. It is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[1]; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ + +static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS]; + +static volatile uint8_t g_irqmap[NR_IRQS]; + +/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register + * content. + */ + +static uint32_t g_intenable[1]; + +/* Bitsets for free, unallocated CPU interrupts available to peripheral + * devices. + */ + +static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET; + +/* Bitsets for each interrupt priority 1-5 */ + +static const uint32_t g_priority[5] = +{ + ESP32S3_INTPRI1_MASK, + ESP32S3_INTPRI2_MASK, + ESP32S3_INTPRI3_MASK, + ESP32S3_INTPRI4_MASK, + ESP32S3_INTPRI5_MASK +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s3_intinfo + * + * Description: + * Return the CPU interrupt map of the given CPU and the register map + * of the given peripheral. + * + ****************************************************************************/ + +static void esp32s3_intinfo(int cpu, int periphid, + uintptr_t *regaddr, uint8_t **intmap) +{ + *regaddr = CORE0_MAP_REGADDR(periphid); + *intmap = g_cpu0_intmap; +} + +/**************************************************************************** + * Name: esp32s3_getcpuint + * + * Description: + * Get a free CPU interrupt for a peripheral device. This function will + * not ignore all of the pre-allocated CPU interrupts for internal + * devices. + * + * Input Parameters: + * intmask - mask of candidate CPU interrupts. The CPU interrupt will be + * be allocated from free interrupts within this set + * + * Returned Value: + * On success, a CPU interrupt number is returned. + * A negated errno is returned on failure. + * + ****************************************************************************/ + +static int esp32s3_getcpuint(uint32_t intmask) +{ + uint32_t *freeints; + uint32_t bitmask; + uint32_t intset; + int cpuint; + int ret = -ENOMEM; + int cpu = 0; + + /* Check if there are CPU interrupts with the requested properties + * available. + */ + + cpu = up_cpu_index(); Review comment: Recently we had https://github.com/apache/incubator-nuttx/pull/5264 so we can go with `volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];` even right now. But this is minor comment. It is fine to go with `volatile uint32_t *g_current_regs[1];` for now and rework later -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
