pkarashchenko commented on a change in pull request #5352: URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793675606
########## File path: arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h ########## @@ -0,0 +1,1961 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_UART_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* UART_FIFO_REG register + * FIFO data register + */ + +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) + +/* UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + +#define UART_RXFIFO_RD_BYTE 0x000000ff +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000ff +#define UART_RXFIFO_RD_BYTE_S 0 + +/* UART_INT_RAW_REG register + * Raw interrupt status + */ + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) + +/* UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes + * more times than what reg_active_threshold specifies in light sleeping + * mode. + */ + +#define UART_WAKEUP_INT_RAW (BIT(19)) Review comment: minor ```suggestion #define UART_WAKEUP_INT_RAW BIT(19) ``` here and in other places ########## File path: arch/xtensa/src/esp32s3/hardware/esp32s3_systimer.h ########## @@ -0,0 +1,808 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_systimer.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTIMER_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTIMER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SYSTIMER_CONF_REG register + * Configure system timer clock + */ + +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) + +/* SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + +#define SYSTIMER_CLK_EN (BIT(31)) Review comment: minor ```suggestion #define SYSTIMER_CLK_EN BIT(31) ``` here and in other places ########## File path: arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h ########## @@ -0,0 +1,2761 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* EXTMEM_DCACHE_CTRL_REG register + * ******* Description *********** + */ + +#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) + +/* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W; bitpos: [4:3]; default: 0; + * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: + * 64 bytes + */ + +#define EXTMEM_DCACHE_BLOCKSIZE_MODE 0x00000003 +#define EXTMEM_DCACHE_BLOCKSIZE_MODE_M (EXTMEM_DCACHE_BLOCKSIZE_MODE_V << EXTMEM_DCACHE_BLOCKSIZE_MODE_S) +#define EXTMEM_DCACHE_BLOCKSIZE_MODE_V 0x00000003 +#define EXTMEM_DCACHE_BLOCKSIZE_MODE_S 3 + +/* EXTMEM_DCACHE_SIZE_MODE : R/W; bitpos: [2]; default: 0; + * The bit is used to configure cache memory size.0: 32KB, 1: 64KB + */ + +#define EXTMEM_DCACHE_SIZE_MODE (BIT(2)) Review comment: minor ```suggestion #define EXTMEM_DCACHE_SIZE_MODE BIT(2) ``` here and in other places ########## File path: arch/xtensa/src/esp32s3/hardware/esp32s3_iomux.h ########## @@ -0,0 +1,467 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_iomux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_IOMUX_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_IOMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +/**************************************************************************** + * Pre-preprocessor Definitions + ****************************************************************************/ + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ + +/* Output enable in sleep mode */ + +#define SLP_OE (BIT(0)) Review comment: minor ```suggestion #define SLP_OE BIT(0) ``` here and in other places ########## File path: arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h ########## @@ -0,0 +1,5795 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The value that needs to be written to RTC_CNTL_WDT_WKEY to + * write-enable the wdt registers + */ + +#define RTC_CNTL_WDT_WKEY_VALUE 0x50d83aa1 + +/* RTC_CNTL_RTC_OPTIONS0_REG register + * RTC common configure register + */ + +#define RTC_CNTL_RTC_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) + +/* RTC_CNTL_SW_SYS_RST : WO; bitpos: [31]; default: 0; + * SW system reset + */ + +#define RTC_CNTL_SW_SYS_RST (BIT(31)) Review comment: minor ```suggestion #define RTC_CNTL_SW_SYS_RST BIT(31) ``` here and in other places ########## File path: boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3.ld ########## @@ -0,0 +1,269 @@ +/**************************************************************************** + * boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_flash.ld + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +_diram_i_start = 0x40378000; + +SECTIONS +{ + /* Send .iram0 code to iram */ + + .iram0.vectors : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to IRAM. */ + + _init_start = ABSOLUTE(.); + + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + + . = 0x0; + KEEP (*(.window_vectors.text)); + . = 0x180; + KEEP (*(.xtensa_level2_vector.text)); + . = 0x1c0; + KEEP (*(.xtensa_level3_vector.text)); + . = 0x200; + KEEP (*(.xtensa_level4_vector.text)); + . = 0x240; + KEEP (*(.xtensa_level5_vector.text)); + . = 0x280; + KEEP (*(.debug_exception_vector.text)); + . = 0x2c0; + KEEP (*(.nmi_vector.text)); + . = 0x300; + KEEP (*(.kernel_exception_vector.text)); + . = 0x340; + KEEP (*(.user_exception_vector.text)); + . = 0x3c0; + KEEP (*(.double_exception_vector.text)); + . = 0x400; + *(.*_vector.literal) + + . = ALIGN (16); + + *(.entry.text) + *(.init.literal) + *(.init) + } > iram0_0_seg + + .iram0.text : + { + /* Code marked as running out of IRAM */ + + *(.iram1 .iram1.*) + + /* align + add 16B for CPU dummy speculative instr. fetch */ + + . = ALIGN(4) + 16; + + _iram_text = ABSOLUTE(.); + } > iram0_0_seg + + .dram0.dummy (NOLOAD) : + { + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; + } > dram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + /* .bss initialized on power-up */ + + . = ALIGN (8); + _sbss = ABSOLUTE(.); + + *(.bss .bss.*) + *(COMMON) + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.share.mem) + *(.gnu.linkonce.b.*) + + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > dram0_0_seg + + .noinit (NOLOAD) : + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + . = ALIGN(4); + + *(.noinit .noinit.*) + + . = ALIGN(4); + } > dram0_0_seg + + .dram0.data : + { + /* .data initialized on power-up in ROMed configurations. */ + + _sdata = ABSOLUTE(.); + KEEP (*(.data)) + KEEP (*(.data.*)) + KEEP (*(.gnu.linkonce.d.*)) + KEEP (*(.data1)) + KEEP (*(.sdata)) + KEEP (*(.sdata.*)) + KEEP (*(.gnu.linkonce.s.*)) + KEEP (*(.sdata2)) + KEEP (*(.sdata2.*)) + KEEP (*(.gnu.linkonce.s2.*)) + KEEP (*(.jcr)) + *(.dram1 .dram1.*) + + _edata = ABSOLUTE(.); + . = ALIGN(4); + + /* Heap starts at the end of .data */ + + _sheap = ABSOLUTE(.); + } > dram0_0_seg + + .flash.text : + { + _stext = .; + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /* CPU will try to prefetch up to 16 bytes of instructions. + * This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + + . += 16; + + _etext = .; + } > default_code_seg + + .flash_rodata_dummy (NOLOAD) : + { + /* This dummy section represents the .flash.text section but in default_rodata_seg. + * Thus, it must have its alignment and (at least) its size. + */ + + /* Start at the same alignment constraint than .flash.text */ + + . = ALIGN(ALIGNOF(.flash.text)); + + /* Create an empty gap as big as .flash.text section */ + + . = SIZEOF(.flash.text); + + /* Prepare the alignment of the section above. Few bytes (0x20) must be + * added for the mapping header. + */ + + . = ALIGN(0x10000) + 0x20; + _rodata_reserved_start = .; + } > default_rodata_seg + + .flash.rodata : ALIGN(0x10) + { + _srodata = ABSOLUTE(.); + + *(.rodata) + *(.rodata.*) + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame) + + . = (. + 3) & ~ 3; Review comment: Maybe just `. = ALIGN(4);`? ########## File path: arch/xtensa/src/esp32s3/hardware/esp32s3_system.h ########## @@ -0,0 +1,1757 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_system.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTEM_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTEM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SYSTEM_CORE_1_CONTROL_0_REG register + * Core0 control regiter 0 + */ + +#define SYSTEM_CORE_1_CONTROL_0_REG (DR_REG_SYSTEM_BASE + 0x0) + +/* SYSTEM_CONTROL_CORE_1_RESETING : R/W; bitpos: [2]; default: 1; + * Set 1 to let core1 reset + */ + +#define SYSTEM_CONTROL_CORE_1_RESETING (BIT(2)) Review comment: minor ```suggestion #define SYSTEM_CONTROL_CORE_1_RESETING BIT(2) ``` here and in other places ########## File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.h ########## @@ -0,0 +1,485 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H +#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/arch.h> +#include <nuttx/irq.h> + +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include <debug.h> + +#include "chip.h" + +#include "hardware/esp32s3_uart.h" +#include "hardware/esp32s3_gpio_sigmap.h" + +#include "esp32s3_irq.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum uart_sclk +{ + APB_CLK = 1, /* 80 MHz */ + CLK_8, /* 8 MHz */ + XTAL_CLK +}; + +enum uart_parity +{ + UART_PARITY_DISABLE, + UART_PARITY_ODD, + UART_PARITY_EVEN +}; + +enum uart_data_length +{ + UART_DATA_5_BITS, + UART_DATA_6_BITS, + UART_DATA_7_BITS, + UART_DATA_8_BITS +}; + +enum uart_stop_length +{ + UART_STOP_BITS_1 = 0x1, /* Stop bit: 1 bit */ + UART_STOP_BITS_2 = 0x3, /* Stop bit: 2 bits */ Review comment: @gustavonihei could you please fix this? -- This is an automated message from the Apache Git Service. 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