gustavonihei commented on a change in pull request #5352: URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793709230
########## File path: arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h ########## @@ -0,0 +1,1961 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_UART_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* UART_FIFO_REG register + * FIFO data register + */ + +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) + +/* UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + +#define UART_RXFIFO_RD_BYTE 0x000000ff +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000ff +#define UART_RXFIFO_RD_BYTE_S 0 + +/* UART_INT_RAW_REG register + * Raw interrupt status + */ + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) + +/* UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes + * more times than what reg_active_threshold specifies in light sleeping + * mode. + */ + +#define UART_WAKEUP_INT_RAW (BIT(19)) Review comment: @pkarashchenko These are auto-generated, so I prefer to leave these as-is to avoid additional work for every other future header. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
