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commit 4a468b8d3b8c4acedb0d94ac45d7b63a0d33d7af Author: Ville Juven <[email protected]> AuthorDate: Thu Jun 1 15:37:57 2023 +0300 riscv/saveusercontext: Fix FPU state save --- arch/risc-v/src/common/riscv_saveusercontext.S | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/risc-v/src/common/riscv_saveusercontext.S b/arch/risc-v/src/common/riscv_saveusercontext.S index b89508b3dd..bbdeca21e0 100644 --- a/arch/risc-v/src/common/riscv_saveusercontext.S +++ b/arch/risc-v/src/common/riscv_saveusercontext.S @@ -56,7 +56,10 @@ up_saveusercontext: REGSTORE sp, REG_X2(a0) /* original SP */ REGSTORE x1, REG_EPC(a0) - riscv_savefpu a0 +#ifdef CONFIG_ARCH_FPU + addi a0, a0, INT_XCPT_SIZE /* Save FPU after integer regs */ + riscv_savefpu a0 +#endif li a0, 0 jr ra
