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commit 31476bcb34d039ba7fb42a142e7c9adacebf8f31
Author: Tiago Medicci Serrano <tiago.medi...@espressif.com>
AuthorDate: Tue Aug 8 08:48:43 2023 -0300
esp32s3/rtc: Initialize RTC subsystem
RTC subsystem controls not only the RTC itself but functions that
use RTC-enabled features like Bluetooth and Wi-Fi. Initialization
must be performed during the system start-up.
---
arch/xtensa/src/esp32s3/esp32s3_rtc.c | 46 ++++++++++-----
arch/xtensa/src/esp32s3/esp32s3_rtc.h | 22 ++-----
arch/xtensa/src/esp32s3/esp32s3_start.c | 6 ++
arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h | 60 +++++++++++++++++++
arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h | 62 ++++++++++++++++++++
arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h | 80 ++++++++++++++++++++++++++
6 files changed, 245 insertions(+), 31 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc.c
b/arch/xtensa/src/esp32s3/esp32s3_rtc.c
index 730e5dbaa4..ebc18ee078 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_rtc.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_rtc.c
@@ -34,6 +34,9 @@
#include "esp32s3_clockconfig.h"
#include "esp32s3_rt_timer.h"
+#include "hardware/esp32s3_bb.h"
+#include "hardware/esp32s3_nrx.h"
+#include "hardware/esp32s3_fe.h"
#include "hardware/esp32s3_rtccntl.h"
#include "hardware/esp32s3_rtc_io.h"
#include "hardware/esp32s3_system.h"
@@ -111,10 +114,6 @@
#define RCT_FAST_D256_FREQ_APPROX (RTC_FAST_CLK_FREQ_APPROX / 256)
#define RTC_SLOW_CLK_FREQ_APPROX 32768
-/* Number of fractional bits in values returned by rtc_clk_cal */
-
-#define RTC_CLK_CAL_FRACT 19
-
/* Disable logging from the ROM code. */
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16))
@@ -421,10 +420,30 @@ extern void ets_update_cpu_frequency(uint32_t
ticks_per_us);
static void IRAM_ATTR
esp32s3_rtc_sleep_pu(struct esp32s3_rtc_sleep_pu_config_s cfg)
{
+ REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG,
+ RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
+ REG_SET_FIELD(RTC_CNTL_RTC_PWC_REG,
+ RTC_CNTL_RTC_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
+ REG_SET_FIELD(RTC_CNTL_RTC_PWC_REG,
+ RTC_CNTL_RTC_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
+ REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG,
+ SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
+ REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG,
+ SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
+ REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG,
+ SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
+ REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
+ REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
+ REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
+ REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
+ REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
+ REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
+ REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
+
if (cfg.sram_fpu)
{
- REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP,
- SYSCON_SRAM_POWER_UP);
+ REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG,
+ SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
}
else
{
@@ -1496,6 +1515,14 @@ void IRAM_ATTR esp32s3_rtc_init(void)
/* set wifi timer */
+ REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, 1);
+ REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, 1);
+
+ /* set bt timer */
+
+ REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, 1);
+ REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, 1);
+
/* Reset RTC bias to default value (needed if waking up from deep sleep) */
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP,
@@ -2507,13 +2534,6 @@ int up_rtc_settime(const struct timespec *ts)
int up_rtc_initialize(void)
{
-#ifndef CONFIG_PM
- /* Initialize RTC controller parameters */
-
- esp32s3_rtc_init();
- esp32s3_rtc_clk_set();
-#endif
-
g_rtc_save = &rtc_saved_data;
/* If saved data is invalid, clear offset information */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc.h
b/arch/xtensa/src/esp32s3/esp32s3_rtc.h
index 21d57aef4e..dae9db3135 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_rtc.h
+++ b/arch/xtensa/src/esp32s3/esp32s3_rtc.h
@@ -64,6 +64,10 @@ extern "C"
#define EXT_OSC_FLAG BIT(3)
+/* Number of fractional bits in values returned by rtc_clk_cal */
+
+#define RTC_CLK_CAL_FRACT 19
+
/****************************************************************************
* Public Types
****************************************************************************/
@@ -298,24 +302,6 @@ void esp32s3_rtc_update_to_xtal(int freq, int div);
void esp32s3_rtc_bbpll_enable(void);
-/****************************************************************************
- * Name: esp32s3_rtc_bbpll_configure
- *
- * Description:
- * Configure main XTAL frequency values according to pll_freq.
- *
- * Input Parameters:
- * xtal_freq - XTAL frequency values
- * pll_freq - PLL frequency values
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
-static void IRAM_ATTR esp32s3_rtc_bbpll_configure(
- enum esp32s3_rtc_xtal_freq_e xtal_freq, int pll_freq);
-
/****************************************************************************
* Name: esp32s3_rtc_clk_set
*
diff --git a/arch/xtensa/src/esp32s3/esp32s3_start.c
b/arch/xtensa/src/esp32s3/esp32s3_start.c
index d2b0bb9c58..0db7633620 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_start.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_start.c
@@ -38,6 +38,7 @@
#include "esp32s3_clockconfig.h"
#include "esp32s3_region.h"
#include "esp32s3_periph.h"
+#include "esp32s3_rtc.h"
#include "esp32s3_spiram.h"
#include "esp32s3_wdt.h"
#ifdef CONFIG_BUILD_PROTECTED
@@ -322,6 +323,11 @@ void noreturn_function IRAM_ATTR __esp32s3_start(void)
esp32s3_wdt_early_deinit();
+ /* Initialize RTC controller parameters */
+
+ esp32s3_rtc_init();
+ esp32s3_rtc_clk_set();
+
/* Set CPU frequency configured in board.h */
esp32s3_clockconfig();
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h
b/arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h
new file mode 100644
index 0000000000..16bce13ae8
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h
@@ -0,0 +1,60 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_BB_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_BB_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Some of the baseband control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
+
+#define BB_FFT_FORCE_PU (BIT(3))
+#define BB_FFT_FORCE_PU_M (BIT(3))
+#define BB_FFT_FORCE_PU_V 1
+#define BB_FFT_FORCE_PU_S 3
+
+#define BB_FFT_FORCE_PD (BIT(2))
+#define BB_FFT_FORCE_PD_M (BIT(2))
+#define BB_FFT_FORCE_PD_V 1
+#define BB_FFT_FORCE_PD_S 2
+
+#define BB_DC_EST_FORCE_PU (BIT(1))
+#define BB_DC_EST_FORCE_PU_M (BIT(1))
+#define BB_DC_EST_FORCE_PU_V 1
+#define BB_DC_EST_FORCE_PU_S 1
+
+#define BB_DC_EST_FORCE_PD (BIT(0))
+#define BB_DC_EST_FORCE_PD_M (BIT(0))
+#define BB_DC_EST_FORCE_PD_V 1
+#define BB_DC_EST_FORCE_PD_S 0
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_BB_H */
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h
b/arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h
new file mode 100644
index 0000000000..35bfb1361f
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h
@@ -0,0 +1,62 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_FE_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_FE_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Some of the RF frontend control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
+
+#define FE_IQ_EST_FORCE_PU (BIT(5))
+#define FE_IQ_EST_FORCE_PU_M (BIT(5))
+#define FE_IQ_EST_FORCE_PU_V 1
+#define FE_IQ_EST_FORCE_PU_S 5
+
+#define FE_IQ_EST_FORCE_PD (BIT(4))
+#define FE_IQ_EST_FORCE_PD_M (BIT(4))
+#define FE_IQ_EST_FORCE_PD_V 1
+#define FE_IQ_EST_FORCE_PD_S 4
+
+#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
+
+#define FE2_TX_INF_FORCE_PU (BIT(10))
+#define FE2_TX_INF_FORCE_PU_M (BIT(10))
+#define FE2_TX_INF_FORCE_PU_V 1
+#define FE2_TX_INF_FORCE_PU_S 10
+
+#define FE2_TX_INF_FORCE_PD (BIT(9))
+#define FE2_TX_INF_FORCE_PD_M (BIT(9))
+#define FE2_TX_INF_FORCE_PD_V 1
+#define FE2_TX_INF_FORCE_PD_S 9
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_FE_H */
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h
b/arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h
new file mode 100644
index 0000000000..0937525824
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h
@@ -0,0 +1,80 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_NRX_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_NRX_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Some of the WiFi RX control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
+
+#define NRX_CHAN_EST_FORCE_PU (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_V 1
+#define NRX_CHAN_EST_FORCE_PU_S 7
+
+#define NRX_CHAN_EST_FORCE_PD (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_V 1
+#define NRX_CHAN_EST_FORCE_PD_S 6
+
+#define NRX_RX_ROT_FORCE_PU (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_V 1
+#define NRX_RX_ROT_FORCE_PU_S 5
+
+#define NRX_RX_ROT_FORCE_PD (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_V 1
+#define NRX_RX_ROT_FORCE_PD_S 4
+
+#define NRX_VIT_FORCE_PU (BIT(3))
+#define NRX_VIT_FORCE_PU_M (BIT(3))
+#define NRX_VIT_FORCE_PU_V 1
+#define NRX_VIT_FORCE_PU_S 3
+
+#define NRX_VIT_FORCE_PD (BIT(2))
+#define NRX_VIT_FORCE_PD_M (BIT(2))
+#define NRX_VIT_FORCE_PD_V 1
+#define NRX_VIT_FORCE_PD_S 2
+
+#define NRX_DEMAP_FORCE_PU (BIT(1))
+#define NRX_DEMAP_FORCE_PU_M (BIT(1))
+#define NRX_DEMAP_FORCE_PU_V 1
+#define NRX_DEMAP_FORCE_PU_S 1
+
+#define NRX_DEMAP_FORCE_PD (BIT(0))
+#define NRX_DEMAP_FORCE_PD_M (BIT(0))
+#define NRX_DEMAP_FORCE_PD_V 1
+#define NRX_DEMAP_FORCE_PD_S 0
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_NRX_H */
