lhutton1 commented on code in PR #16966:
URL: https://github.com/apache/tvm/pull/16966#discussion_r1598578740
##########
src/tir/transforms/vectorize_loop.cc:
##########
@@ -72,6 +72,126 @@ inline PrimExpr BroadcastTo(PrimExpr e, int lanes, bool
is_scalable) {
return Broadcast(e, CreateNewLanes(is_scalable, lanes));
}
+bool EnableBufferLevelPredication() {
Review Comment:
Thanks, that makes sense. Do you know if there is any general infrastructure
for keep track of the current target (which takes into account this override
functionality) from within a pass? Otherwise I feel we will be duplicating this
functionality in multiple places. I was thinking something similar to:
`LexicalOnDeviceMixin` (assuming I understood it correctly)
##########
src/target/llvm/codegen_llvm.cc:
##########
@@ -1768,11 +1774,17 @@ llvm::Value* CodeGenLLVM::VisitExpr_(const
BufferLoadNode* op) {
std::vector<llvm::Value*> loads;
- auto make_load = [this, &loads](TypedPointer buffer_ptr, int /* subelement_i
*/, int alignment,
- bool is_volatile) {
+ auto make_load = [this, &loads](TypedPointer buffer_ptr, int /* subelement_i
*/,
+ llvm::Value* predicate, int alignment, bool
is_volatile) {
#if TVM_LLVM_VERSION >= 110
- auto load = builder_->CreateAlignedLoad(buffer_ptr.type, buffer_ptr.addr,
- llvm::Align(alignment),
is_volatile);
+ llvm::Instruction* load = nullptr;
+ if (predicate != NULL) {
+ load = builder_->CreateMaskedLoad(buffer_ptr.type, buffer_ptr.addr,
llvm::Align(alignment),
+ predicate);
Review Comment:
Good point, thanks. I took a look at MaskedLoad in LLVM and it doesn't seem
possible to create a volatile masked load, I'll throw an exception for now.
##########
python/tvm/tir/buffer.py:
##########
@@ -141,6 +141,57 @@ def vstore(self, begin, value):
begin = (begin,) if isinstance(begin, (int, PrimExpr)) else begin
return _ffi_api.BufferVStore(self, begin, value) # type: ignore
+ def load(self, indices, predicate=None):
Review Comment:
We did look at reusing these but decided against it since the vload/vstore
api doesn't let you specify the "indices" argument of the underlying buffer
load/store which can limit expressing more complex (e.g. non-consecutive)
accesses
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