cbalint13 commented on PR #17853:
URL: https://github.com/apache/tvm/pull/17853#issuecomment-2816092581
Hi @jerryzj !
LLVM side (implicitly TVM) is aware of this already:
```
$ cat tvm-llvm-rvv.py
#!/usr/bin/python3
import tvm
target = tvm.target.Target("llvm -device=riscv_cpu
-mtriple=riscv32-linux-gnu -mcpu=generic-rv32 -mattr=+i,+m,+v")
print("LLVM [%s]" % target)
print("LLVM features: %s" %
(tvm.target.codegen.llvm_get_cpu_features(target)))
```
```
$ ./tvm-llvm-rvv.py
LLVM [llvm -keys=riscv_cpu,cpu -device=riscv_cpu -mattr=+i,+m,+v
-mcpu=generic-rv32 -mtriple=riscv32-linux-gnu]
LLVM features: {'zve64x', 'zve32f', 'zve64f', 'zmmul', 'zve64d', 'f',
'zicsr', 'd', 'optimized-nf2-segment-load-store', 'm', 'zve32x', 'zvl32b', 'v',
'zvl128b', 'zvl64b', '32bit', 'i'}
```
Notice the presence of ```zvl128b```, that was added due to ```+v```
presence, so this will be properly picked up anyway.
---
**BUT**, please note that in the case of no ```+v``` (absence) we still
need a *default* TVM vector width, and this one has nothing to do with the ISA
anymore, but yes let's settle it to 128 (down from current 256).
I am just working right now on refactoring RISCV target to also enable the
SVE predication, will reference this PR.
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