cbalint13 commented on PR #17853: URL: https://github.com/apache/tvm/pull/17853#issuecomment-2816682189
> If there is no `v`, `zve*` or other `zvl` specified, meaning that current CPU is not supporting vector operations hence no vector registers, why not set VLEN to 0? First ```vector_with != VLEN```, it **only becomes** equivalent with VLEN in case of SVE support (WiP), where it will be used. There is a refactor effort of what is described here: https://github.com/apache/tvm/pull/17859 , making things clear. --- To recap, TVM is relaying on LLVM (well maintained) as root of trust , it extract "arch knowledge" from, **not vice-versa**: Few scenarios for ```riscv``` case: 1. If no ```v``` present, or whatever other arch it is, we still need a ```vector_with``` for TVM alignment hints (but doesn't really matter). 2. If only ```v``` is present, but no extra attributes, then a ```zvl128b``` will be implicitly present, it will be added by LLVM library (due to ISA spec you mentioned) 3. If ```v``` is present, and extra attributes like ```+zvl1024b``` as override, then this will be picked up (from LLVM library). 4. If no attributes are present but cpu is a known vendor one like ```-mcpu=sifive-x280``` then ```zvl512b``` will be picked up from LLVM library side. TVM only extracts ```zvl<XXX>b``` from LLVM library (riscv case), if they do something wrong TVM is also doing wrong. See full scenarios that are checked as target tests: [tests/python/target/test_riscv_features.py](https://github.com/apache/tvm/blob/4bbdd8c12dd8dfbfbaa1fd86081dd2ca5992eaa8/tests/python/target/test_riscv_features.py) One can use the sample code (posted here on top) to check what kind of features for various targets are yielded. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
