giuseros commented on a change in pull request #5754:
URL: https://github.com/apache/incubator-tvm/pull/5754#discussion_r440055355
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File path: topi/python/topi/arm_cpu/conv2d_alter_op.py
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@@ -235,5 +239,37 @@ def _alter_conv2d_layout(attrs, inputs, tinfos, out_type):
new_attrs['out_layout'], out_dtype], topi_tmpl)
dispatch_ctx.update(target, new_workload, cfg)
return relay.nn.contrib_depthwise_conv2d_nchwc(*inputs, **new_attrs)
+ if topi_tmpl == "conv2d_NHWC_quantized.arm_cpu":
+ assert (data.dtype == 'int8' and kernel.dtype == 'int8' or
+ data.dtype == 'uint8' and kernel.dtype == 'uint8')
+ CO, IC, KH, KW = get_const_tuple(kernel.shape)
+
+ K = KH * KW * IC
+ N = CO
+
+ pad_k = 0
+ pad_n = 0
+
+ if N % 4 != 0:
+ pad_n = 4 - (N % 4)
+
+ if K % 16 != 0:
+ pad_k = 16 - (K % 16)
+
+ N_padded = N + pad_n
+ K_padded = K + pad_k
+
+ kernel_expr = relay.nn.contrib_conv2d_gemm_weight_transform(inputs[1])
Review comment:
I wasn't able to find any. The idea is similar to Winograd, but winograd
uses tiling, while here I am [block transposing and
interleaving](https://discuss.tvm.ai/uploads/default/original/2X/6/635d11f9639f849945788694f64346ca2bdcd461.png).
We would need the kernel layout only to assert against the wrong one. So
yes, if you think it could be useful, I can do that.
As for changing the name to `contrib_conv2d_gemm_hwio_weight_transform`, I
can easily implement that, but this means that if we want to suport NCHW in the
future we will have to change it again (and I think this is why they didn't do
that for Winograd)
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