junrushao1994 commented on code in PR #80: URL: https://github.com/apache/tvm-rfcs/pull/80#discussion_r899863568
########## rfcs/0077-async-pipeline.md: ########## @@ -0,0 +1,523 @@ +- Feature Name: Asynchronous stage in software pipeline +- Start Date: (2022-06-17) + +# Summary +This RFC proposes two TIR intrinsics and an additional annotation to the TIR software pipeline transform, to express asynchrony within **the device code**. +Asynchrony is prevalent on the host (runtime) side, and this proposal is the first step toward bringing the notion of an asynchronous operation in the +generated code. + +The most important component we should agree on is the model of synchronization: Coming up with a design that is general enough to be useful for diverse backends, while making sure that the chosen design can be translated to a low-level synchronization model of a particular backend, is highly non-trivial. +The approach described in this document is motivated by a use case for NVIDIA GPUs, but we took some cares so that the design can be adopted by other backends. The proposed model may have diverged from conventional ones, but we believe that this is a good for the TIR software pipeline specifically. Review Comment: Let's elaborate our capability a bit more, for example, we support synchronization between tensor unit + vector unit + dma engine + etc -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
