erwango commented on code in PR #12756:
URL: https://github.com/apache/tvm/pull/12756#discussion_r970431895
##########
apps/microtvm/zephyr/template_project/app-overlay/nucleo_l4r5zi.overlay:
##########
@@ -21,3 +21,29 @@
&rcc {
clock-frequency = <DT_FREQ_M(120)>;
};
+
+/* Set PLL, where:
+
+ VCO freq = PLL clock input freq (HSI: 16 MHz) * N / M,
+ Core freq = VCO freq / R,
+ PLL48M1CLK freq = VCO freq / Q, and
+ PLLSAI3CLK freq = VCO freq / P,
+
+ Hence, since div-q = 2 => Q = 6 and div-p = 7 => P = 7:
+
+ VCO freq = 16 * 30 / 2 = 240 MHz
+
+ Core freq = 240 MHz / 2 = 120 MHz
+ PLL48M1CLK freq = 240 MHz / PLLQ = 40 MHz
+ PLLSAI3CLK freq = 240 MHz / PLLP = 34.28571 MHz
+*/
+
+&pll {
+ div-m = <2>;
+ mul-n = <30>;
+ div-p = <7>;
+ div-q = <2>;
Review Comment:
I oversaw this indeed. Prop values are the values to be used in the
computation and driver makes the translation in register space.
Regarding the need for a 48MHz this depends on your needs. If required this
can impose the use of a 96MHz Max freq on core. But note that USB, entropy and
sdmmc are the only consumer of 48MHz clock available today in main zephyr tree.
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