areusch commented on code in PR #13514:
URL: https://github.com/apache/tvm/pull/13514#discussion_r1060982279
##########
src/meta_schedule/schedule_rule/schedule_rule.cc:
##########
@@ -251,6 +251,34 @@ Array<ScheduleRule> ScheduleRule::DefaultHexagon() {
};
}
+Array<ScheduleRule> ScheduleRule::DefaultMicro() {
+ return {
+ ScheduleRule::AutoInline(
+ /*into_producer=*/false,
+ /*into_consumer=*/true,
+ /*inline_const_tensor=*/true,
+ /*disallow_if_then_else=*/true,
+ /*require_injective=*/true,
+ /*require_ordered=*/true,
+ /*disallow_op=*/Array<String>{"tir.exp"}),
+ ScheduleRule::MultiLevelTiling(
+ /*structure=*/"SSRSRS",
+ /*tile_binds=*/NullOpt,
+ /*max_innermost_factor=*/Integer(64),
+ /*vector_load_lens=*/NullOpt,
+ /*reuse_read=*/NullOpt,
+ /*reuse_write=*/
+ Map<String, ObjectRef>{{"req", String("may")},
+ {"levels", Array<Integer>{1, 2}},
+ {"scope", String("global")}}),
+ ScheduleRule::ParallelizeVectorizeUnroll(
Review Comment:
can you try excluding this schedule rule and see if that allows you to
remove `num-cores` Target attr?
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