On Sat, Apr 07, 2018 at 06:21:15PM -0800, Mychaela Falconia wrote:

> And we still need to fix and close the sleep mode bug.  I have a high
> confidence in my current hypothesis that FDP driving the flash chip's
> reset line is the culprit, but it looks like we won't be able to test
> it empirically until we build our next board, be it FCDEV3Bv2 or the
> first version of the HSMBP.

Hi Mychaela,

Looking at the project in Altium, it seems the signal trace from D5 to
U201 sits at the bottom layer. I think it might be not too difficult to
do some surgery to cut the trace in the middle and pull it up elsewhere.
I might try that on my FCDEV3B unless you want to try it on one of the
boards you have.

BTW is there an easter egg in the PCB layout? I can read "TimLee Allen
Shawn Jean Shanny" above the SIM holder.

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