Hi! The BKDG rev. 3.08 for AMD Family 0Fh states that it is possible to use a CAR area with a size of 64K in section 13.16 "Cache Initialization For General Storage During Boot". It also says that during DRAM training CAR size must be reduced. For DDR training, 256 cache lines with L1 cache tag indexes 00h-FFh are reserved and must not be used as CAR. The text then refers to the AMD64 Arch Programmers Manual Vol. 2 for more details on L1 function. However, I couldn't find any explanation why L1 cache tag indexes 00h-FFh correspond to address space C0000h-C3FFFh when fixed size MTRRs are active.
Explanations would be very welcome. Regards, Carl-Daniel -- coreboot mailing list [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
