On 15.01.2008 20:36, Rudolf Marek wrote: > I just can explain in general what addresses are "forbidden". > > L1 cache is 64KB 2-way associative with 64B block size. > > This means 6 bits for data (to address the 64Bytes) and for the cache > index we > have 65536 / ( 2 * 64) = 512 rows so we have 9 bits for this, rest is > TAG. > So the 32 bit memory address would look like this when cut: > > 31st ..... TAG ..... 14th .... INDEX ..... 5th block addr. > > So "forbidden" addresses are all from range which will hit first 256 cache > lines, so address from bit 0 to bit INDEX - 1 (13rd bit) > > (X means dontcare 4 bits, x is dontcare one bit) > > xxxx x000 0000 00xx xxxx to xxxx x011 1111 11xx xxxx > > Which for it turns out anything in the address range XXXX0000 - > XXXX3FFF will > hit first 256 cache lines. Marc suggest that this is SW issue and not > a HW issue > so perhaps we can ignore this ;) but anyway, it is always good to > explain why > this addresses - I hope there is no mistake in my calculations.
Great explanation, thanks! Something like this should appear in the BKDG. Regards, Carl-Daniel -- coreboot mailing list [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
