ron minnich wrote:
We're still far too slow, perhaps because we are not caching ROM?
Correct. Here is a patch that changes that. BUT, here is a problem here. Due to some cache coherency snoop problems across pci we need the ROM cache properties to be write-serialize + cache disabled.
My suggestion is to reset the ROM cache properties in stage2 once code is executing in memory. The problem is that stage2 returns to stage1 to load the payload. v3 would be slow again trying to decompress the payload.
I don't have any good ideas to fix this yet. I don't know if any other systems will have similar problems with going back to the ROM to load payloads. Most BIOS "shadow" and this isn't an issues. It isn't an issue in v2 because the payload load code is in memory.
Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:[EMAIL PROTECTED] http://www.amd.com/embeddedprocessors
Cache the ROM to speed up stage2 and payload decompression. Due to some cache coherency snoop problems across pci we need the ROM cache properties to be write-serialize + cache disabled by runtime. Signed-off by: Marc Jones <[EMAIL PROTECTED]> Index: coreboot-v3/northbridge/amd/geodelx/geodelxinit.c =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/geodelxinit.c 2008-02-04 13:35:52.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-02-04 13:36:12.000000000 -0700 @@ -658,7 +658,7 @@ #define SYSMEM_RCONF_WRITETHROUGH 8 #define DEVRC_RCONF_DEFAULT 0x21 #define ROMBASE_RCONF_DEFAULT 0xFFFC0000 -#define ROMRC_RCONF_DEFAULT 0x25 +#define ROMRC_RCONF_DEFAULT 0x04 /** * TODO.
-- coreboot mailing list [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
