On 05.02.2008 07:31, ron minnich wrote: > I think this is fine but I'd like to fit it into the "stage" > nomenclature, so the numbering fits. > > So which stage is this? I am not sure, I feel like the stage numbering > never quite got finished :-) > > possibly stage 3 is load payload, stage 4 is prepare the machine for a > payload, and stage5 is run the payload? >
Remember that we load stage 2 like a payload, so we'd have execution order stage 0,1,3,4,5,2,3,4,5,realpayload. Stage 2 is also special because it lives completely in RAM, but it calls a lot of functions in bootblock ROM. If we shadow the boot block, most problems should disappear. One thing I didn't understand: Marc Jones wrote: > Due to some cache coherency snoop problems across pci we need the ROM > cache properties to be write-serialize + cache disabled. The data in ROM doesn't change nor do we write to it. So where exactly do we need write snooping and/or write-serialize? Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
