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Hello,
This patch introduces changes for W83627EHF driver. Not only LDN 7 and 9 are
changed, but also a SPI flash interface which has enable on bit1 and not bit0.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Thanks,
Rudolf
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iD8DBQFHt38s3J9wPJqZRNURAmmcAKDTB+NRv9qw6CnuWPuGP95v/Ka13ACfXY6l
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Index: src/superio/winbond/w83627ehg/superio.c
===================================================================
--- src/superio/winbond/w83627ehg/superio.c (revision 3103)
+++ src/superio/winbond/w83627ehg/superio.c (working copy)
@@ -184,11 +184,17 @@
// No 4 { 0,},
{ &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, W83627EHG_GPIO_GAME_MIDI, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
{ &ops, W83627EHG_WDTO_PLED, },
- { &ops, W83627EHG_GPIO_SUSLED, },
{ &ops, W83627EHG_ACPI, },
{ &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
+ { &ops, W83627EHG_GAME, PNP_IO0, { 0x7ff, 0 }, },
+ { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 } , {0x7fe, 0x4}, },
+ { &ops, W83627EHG_GPIO1, },
+ { &ops, W83627EHG_GPIO2, },
+ { &ops, W83627EHG_GPIO3, },
+ { &ops, W83627EHG_GPIO4, },
+ { &ops, W83627EHG_GPIO5, },
+ { &ops, W83627EHG_GPIO6, },
};
static void enable_dev(struct device *dev)
Index: src/superio/winbond/w83627ehg/w83627ehg.h
===================================================================
--- src/superio/winbond/w83627ehg/w83627ehg.h (revision 3103)
+++ src/superio/winbond/w83627ehg/w83627ehg.h (working copy)
@@ -24,10 +24,23 @@
#define W83627EHG_SP1 2 /* Com1 */
#define W83627EHG_SP2 3 /* Com2 */
#define W83627EHG_KBC 5 /* Keyboard & Mouse */
-#define W83627EHG_SFI 6 /* Serial Flash Interface */
#define W83627EHG_GPIO_GAME_MIDI 7 /* GPIO1, GPIO6, Game Port and MIDI Port */
#define W83627EHG_WDTO_PLED 8 /* TODO */
#define W83627EHG_GPIO_SUSLED 9 /* GPIO2, GPIO3, GPIO4, GPIO5 and SUSLED */
#define W83627EHG_ACPI 10 /* ACPI */
#define W83627EHG_HWM 11 /* Hardware Monitor */
+/* virtual devices sharing the enables are encoded as follows:
+ VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
+*/
+
+#define W83627EHG_SFI ((1 << 8) | 6) /* Flash has bit1 as enable */
+#define W83627EHG_GPIO1 W83627EHG_GPIO_GAME_MIDI /* GPIO1 is at LDN 7, bit 0 */
+#define W83627EHG_GAME ((1 << 8) | 7)
+#define W83627EHG_MIDI ((2 << 8) | 7)
+#define W83627EHG_GPIO6 ((3 << 8) | 7)
+
+#define W83627EHG_GPIO2 W83627EHG_GPIO_SUSLED /* GPIO2 is at LDN 9, bit 0 */
+#define W83627EHG_GPIO3 ((1 << 8) | 9)
+#define W83627EHG_GPIO4 ((2 << 8) | 9)
+#define W83627EHG_GPIO5 ((3 << 8) | 9)
--
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