Comment in patch. Tested on dbe62. Note comment w.r.t. regressions,
which we need to fix.
thanks
ron
Change the low level PCI functions to be really low level, callable from any
point, at any time, including stage 1.
Get rid of conf2, nobody will ever use it.
This has been tested on DBE62.
two observations:
1. there is a regression (which I fixed in part) which is printing a lot of garbage somewhere
in stage1
2. there is another regression which is making pci print a lot of debug, regardless of
console print level.
These two issues point out the need to be very careful when accepting 'it compiles' patches.
We need to ensure that any patch that affects more than one mainboard is tested on at least one
mainboard; and to indicate which mainboard they were tested on.
This change will make K8 port easier. Next is to add a find function a la libpayload for low level.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Index: include/device/pci_def.h
===================================================================
--- include/device/pci_def.h (revision 726)
+++ include/device/pci_def.h (working copy)
@@ -481,6 +481,8 @@
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
#define PCI_FUNC(devfn) ((devfn) & 0x07)
#define PCI_BDF(bus,dev,func) ((bus) << 16 | (dev) << 11 | (func) << 8)
+/* bus,devfn pairs are used many places as well */
+#define PCI_BDEVFN(bus,devfn) ((bus) << 16 | (devfn) << 8)
#define PCI_ADDR(bus,dev,func,where) (PCI_BDF((bus),(dev),(func)) << 4 | (where & 0xfff))
#endif /* DEVICE_PCI_DEF_H */
Index: include/device/pci.h
===================================================================
--- include/device/pci.h (revision 726)
+++ include/device/pci.h (working copy)
@@ -49,12 +49,12 @@
/* Common pci bus operations */
struct pci_bus_operations {
- u8 (*read8)(struct bus *pbus, int bus, int devfn, int where);
- u16 (*read16)(struct bus *pbus, int bus, int devfn, int where);
- u32 (*read32)(struct bus *pbus, int bus, int devfn, int where);
- void (*write8)(struct bus *pbus, int bus, int devfn, int where, u8 val);
- void (*write16)(struct bus *pbus, int bus, int devfn, int where, u16 val);
- void (*write32)(struct bus *pbus, int bus, int devfn, int where, u32 val);
+ u8 (*read8)(u32 bdf, int where);
+ u16 (*read16)(u32 bdf, int where);
+ u32 (*read32)(u32 bdf, int where);
+ void (*write8)(u32 bdf, int where, u8 val);
+ void (*write16)(u32 bdf, int where, u16 val);
+ void (*write32)(u32 bdf, int where, u32 val);
};
struct pci_driver {
Index: include/arch/x86/pci_ops.h
===================================================================
--- include/arch/x86/pci_ops.h (revision 726)
+++ include/arch/x86/pci_ops.h (working copy)
@@ -20,7 +20,6 @@
#include <device/device.h>
extern const struct pci_bus_operations pci_cf8_conf1;
-extern const struct pci_bus_operations pci_cf8_conf2;
#if defined(CONFIG_MMCONF_SUPPORT) && (CONFIG_MMCONF_SUPPORT==1)
extern const struct pci_bus_operations pci_ops_mmconf;
Index: device/pci_ops.c
===================================================================
--- device/pci_ops.c (revision 726)
+++ device/pci_ops.c (working copy)
@@ -48,42 +48,48 @@
u8 pci_read_config8(struct device *dev, unsigned int where)
{
- struct bus *pbus = get_pbus(dev);
- return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary,
- dev->path.u.pci.devfn, where);
+ struct bus *pbus = get_pbus(dev);
+ return ops_pci_bus(pbus)->read8(PCI_BDEVFN(dev->bus->secondary,
+ dev->path.u.pci.devfn),
+ where);
}
u16 pci_read_config16(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
- return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary,
- dev->path.u.pci.devfn, where);
+ return ops_pci_bus(pbus)->read16(PCI_BDEVFN(dev->bus->secondary,
+ dev->path.u.pci.devfn),
+ where);
}
u32 pci_read_config32(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
- return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary,
- dev->path.u.pci.devfn, where);
+ return ops_pci_bus(pbus)->read32(PCI_BDEVFN(dev->bus->secondary,
+ dev->path.u.pci.devfn),
+ where);
}
void pci_write_config8(struct device *dev, unsigned int where, u8 val)
{
struct bus *pbus = get_pbus(dev);
- ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary,
- dev->path.u.pci.devfn, where, val);
+ ops_pci_bus(pbus)->write8(PCI_BDEVFN(dev->bus->secondary,
+ dev->path.u.pci.devfn),
+ where, val);
}
void pci_write_config16(struct device *dev, unsigned int where, u16 val)
{
struct bus *pbus = get_pbus(dev);
- ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary,
- dev->path.u.pci.devfn, where, val);
+ ops_pci_bus(pbus)->write16(PCI_BDEVFN(dev->bus->secondary,
+ dev->path.u.pci.devfn),
+ where, val);
}
void pci_write_config32(struct device *dev, unsigned int where, u32 val)
{
struct bus *pbus = get_pbus(dev);
- ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary,
- dev->path.u.pci.devfn, where, val);
+ ops_pci_bus(pbus)->write32(PCI_BDEVFN(dev->bus->secondary,
+ dev->path.u.pci.devfn),
+ where, val);
}
Index: northbridge/amd/geodelx/raminit.c
===================================================================
--- northbridge/amd/geodelx/raminit.c (revision 726)
+++ northbridge/amd/geodelx/raminit.c (working copy)
@@ -66,7 +66,10 @@
for (i = 0; i < ARRAY_SIZE(msrs); i++) {
struct msr msr;
msr = rdmsr(msrs[i]);
- printk(BIOS_DEBUG, "%s (%lx): %x.%x\n", msrnames[i], msrs[i],
+ /* don't change the %p to a %s unless you fix the problem.
+ * in particular, don't change or submit a patch UNLESS YOU TEST IT
+ */
+ printk(BIOS_DEBUG, "%p (%lx): %x.%x\n", msrnames[i], msrs[i],
msr.hi, msr.lo);
}
Index: arch/x86/pci_ops_conf1.c
===================================================================
--- arch/x86/pci_ops_conf1.c (revision 726)
+++ arch/x86/pci_ops_conf1.c (working copy)
@@ -11,48 +11,52 @@
* Functions for accessing PCI configuration space with type 1 accesses
*/
-/* this shit really should come with comments ...this is annoying.
-#if PCI_IO_CFG_EXT == 0
-#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
+/* The EXT is for extended register sets, i.e. chipsets that have more than 8 bits of registers */
+/* Here is one reason that overkill on types can bite you: Suppose we had insisted on u8 for 'where' for years.
+ * We would have to rewrite everything to grow 'where' to 12 bits! There is a reason that C uses 'int'.
+ * It's a good handy type meaning 'value suitable to the native machine register size'
+ * Also note these take a PCI_BDF -- meaning that the 'where' just needs to be 'or'ed in.
+ */
+#define PCI_IO_CFG_EXT 0
+#if PCI_IO_CFG_EXT
+#define CONFIG_CMD(bdf, where) (0x80000000 | (bdf) | (where & ~3))
#else
-#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) )
+#define CONFIG_CMD(bdf, where) (0x80000000 | (bdf) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) )
#endif
-*/
-#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
-static u8 pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, int where)
+static u8 pci_conf1_read_config8(u32 bdf, int where)
{
- outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+ outl(CONFIG_CMD(bdf, where), 0xCF8);
return inb(0xCFC + (where & 3));
}
-static u16 pci_conf1_read_config16(struct bus *pbus, int bus, int devfn, int where)
+static u16 pci_conf1_read_config16(u32 bdf, int where)
{
- outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+ outl(CONFIG_CMD(bdf, where), 0xCF8);
return inw(0xCFC + (where & 2));
}
-static u32 pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, int where)
+static u32 pci_conf1_read_config32(u32 bdf, int where)
{
- outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+ outl(CONFIG_CMD(bdf, where), 0xCF8);
return inl(0xCFC);
}
-static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn, int where, u8 value)
+static void pci_conf1_write_config8(u32 bdf, int where, u8 value)
{
- outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+ outl(CONFIG_CMD(bdf, where), 0xCF8);
outb(value, 0xCFC + (where & 3));
}
-static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, int where, u16 value)
+static void pci_conf1_write_config16(u32 bdf, int where, u16 value)
{
- outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+ outl(CONFIG_CMD(bdf, where), 0xCF8);
outw(value, 0xCFC + (where & 2));
}
-static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, int where, u32 value)
+static void pci_conf1_write_config32(u32 bdf, int where, u32 value)
{
- outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+ outl(CONFIG_CMD(bdf, where), 0xCF8);
outl(value, 0xCFC);
}
Index: arch/x86/pci_ops_conf2.c
===================================================================
--- arch/x86/pci_ops_conf2.c (revision 726)
+++ arch/x86/pci_ops_conf2.c (working copy)
@@ -1,78 +0,0 @@
-#include <console.h>
-#include <device/device.h>
-#include <pciconf.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <types.h>
-#include <io.h>
-
-/*
- * Functions for accessing PCI configuration space with type 2 accesses
- */
-
-#define IOADDR(devfn, where) ((0xC000 | ((devfn & 0x78) << 5)) + where)
-#define DEVFUNC(devfn) (((devfn & 7) << 1) | 0xf0)
-#define SET(bus,devfn) outb(DEVFUNC(devfn), 0xCF8); outb(bus, 0xCFA);
-
-static u8 pci_conf2_read_config8(struct bus *pbus, int bus, int devfn, int where)
-{
- u8 value;
- SET(bus, devfn);
- value = inb(IOADDR(devfn, where));
- outb(0, 0xCF8);
- return value;
-}
-
-static u16 pci_conf2_read_config16(struct bus *pbus, int bus, int devfn, int where)
-{
- u16 value;
- SET(bus, devfn);
- value = inw(IOADDR(devfn, where));
- outb(0, 0xCF8);
- return value;
-}
-
-static u32 pci_conf2_read_config32(struct bus *pbus, int bus, int devfn, int where)
-{
- u32 value;
- SET(bus, devfn);
- value = inl(IOADDR(devfn, where));
- outb(0, 0xCF8);
- return value;
-}
-
-static void pci_conf2_write_config8(struct bus *pbus, int bus, int devfn, int where, u8 value)
-{
- SET(bus, devfn);
- outb(value, IOADDR(devfn, where));
- outb(0, 0xCF8);
-}
-
-static void pci_conf2_write_config16(struct bus *pbus, int bus, int devfn, int where, u16 value)
-{
- SET(bus, devfn);
- outw(value, IOADDR(devfn, where));
- outb(0, 0xCF8);
-}
-
-static void pci_conf2_write_config32(struct bus *pbus, int bus, int devfn, int where, u32 value)
-{
- SET(bus, devfn);
- outl(value, IOADDR(devfn, where));
- outb(0, 0xCF8);
-}
-
-#undef SET
-#undef IOADDR
-#undef DEVFUNC
-
-const struct pci_bus_operations pci_cf8_conf2 = {
- .read8 = pci_conf2_read_config8,
- .read16 = pci_conf2_read_config16,
- .read32 = pci_conf2_read_config32,
- .write8 = pci_conf2_write_config8,
- .write16 = pci_conf2_write_config16,
- .write32 = pci_conf2_write_config32,
-};
-
Index: arch/x86/pci_ops_auto.c
===================================================================
--- arch/x86/pci_ops_auto.c (revision 726)
+++ arch/x86/pci_ops_auto.c (working copy)
@@ -22,7 +22,6 @@
u16 class, vendor;
unsigned bus;
int devfn;
- struct bus pbus; /* Dummy device */
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_DISPLAY_VGA 0x0300
#define PCI_VENDOR_ID_COMPAQ 0x0e11
@@ -30,8 +29,8 @@
#define PCI_VENDOR_ID_MOTOROLA 0x1057
for (bus = 0, devfn = 0; devfn < 0x100; devfn++) {
- class = o->read16(&pbus, bus, devfn, PCI_CLASS_DEVICE);
- vendor = o->read16(&pbus, bus, devfn, PCI_VENDOR_ID);
+ class = o->read16(PCI_BDEVFN(bus, devfn), PCI_CLASS_DEVICE);
+ vendor = o->read16(PCI_BDEVFN(bus, devfn), PCI_VENDOR_ID);
if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) ||
((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) ||
(vendor == PCI_VENDOR_ID_MOTOROLA))) {
@@ -63,21 +62,6 @@
outl(tmp, 0xCF8);
}
- /*
- * Check if configuration type 2 works.
- */
- {
- outb(0x00, 0xCFB);
- outb(0x00, 0xCF8);
- outb(0x00, 0xCFA);
- if ((inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) &&
- pci_sanity_check(&pci_cf8_conf2))
- {
- printk(BIOS_DEBUG, "PCI: Using configuration type 2\n");
- return &pci_cf8_conf2;
- }
- }
-
die("pci_check_direct failed\n");
return NULL;
}
Index: arch/x86/Makefile
===================================================================
--- arch/x86/Makefile (revision 726)
+++ arch/x86/Makefile (working copy)
@@ -182,7 +182,7 @@
compute_ip_checksum.c string.c
STAGE2_ARCH_X86_SRC = archtables.c coreboot_table.c udelay_io.c
-STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c pci_ops_conf2.c
+STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c
STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
ifeq ($(CONFIG_PIRQ_TABLE),y)
--
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