Author: rminnich
Date: 2008-08-11 18:04:38 +0200 (Mon, 11 Aug 2008)
New Revision: 739
Added:
coreboot-v3/southbridge/nvidia/mcp55/ide.c
coreboot-v3/southbridge/nvidia/mcp55/ide.dts
Log:
.c and .dts for mcp55
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Added: coreboot-v3/southbridge/nvidia/mcp55/ide.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/ide.c (rev 0)
+++ coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-08-11 16:04:38 UTC (rev
739)
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <[EMAIL PROTECTED]> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <[EMAIL PROTECTED]> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+#include <msr.h>
+#include <legacy.h>
+#include <device/pci_ids.h>
+#include <statictree.h>
+#include <config.h>
+#include "mcp55.h"
+
+static void ide_init(struct device *dev)
+{
+ struct southbridge_nvidia_mcp55_ide_config *conf =
+ (struct southbridge_nvidia_mcp55_ide_config
*)dev->device_configuration;
+ /* Enable ide devices so the linux ide driver will work */
+ u32 dword;
+ u16 word;
+ u8 byte;
+
+ word = pci_read_config16(dev, 0x50);
+ /* Ensure prefetch is disabled */
+ word &= ~((1 << 15) | (1 << 13));
+ if (conf->ide1_enable) {
+ word |= (1<<0);
+ printk(BIOS_DEBUG, "Enable secondary ide interface\t");
+ }
+ if (conf->ide0_enable) {
+ word |= (1<<1);
+ printk(BIOS_DEBUG, "Enable primary ide interfac\n");
+ }
+
+ word |= (1<<12);
+ word |= (1<<14);
+
+ pci_write_config16(dev, 0x50, word);
+
+
+ byte = 0x20 ; // Latency: 64-->32
+ pci_write_config8(dev, 0xd, byte);
+
+ dword = pci_read_config32(dev, 0xf8);
+ dword |= 12;
+ pci_write_config32(dev, 0xf8, dword);
+#ifdef CONFIG_PCI_ROM_RUN
+ pci_dev_init(dev);
+#endif
+
+#warning set subsystem id on mcp55 ide
+#if 0
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+#endif
+}
+
+struct device_operations mcp55_ide = {
+ .id = {.type = DEVICE_ID_PCI,
+ {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
+ .device = PCI_DEVICE_ID_NVIDIA_MCP55_IDE}}},
+ .constructor = default_device_constructor,
+ .phase3_scan = 0,
+ .phase4_read_resources = pci_dev_read_resources,
+ .phase4_set_resources = pci_dev_set_resources,
+ .phase5_enable_resources = pci_dev_enable_resources,
+ .phase6_init = ide_init,
+ .ops_pci = &pci_dev_ops_pci,
+};
+
Added: coreboot-v3/southbridge/nvidia/mcp55/ide.dts
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/ide.dts
(rev 0)
+++ coreboot-v3/southbridge/nvidia/mcp55/ide.dts 2008-08-11 16:04:38 UTC
(rev 739)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-8 Ronald G. Minnich <[EMAIL PROTECTED]> *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+{
+ device_operations = "mcp55_ide";
+
+ /* IDE: enable MCP55 IDE. There may be a different IDE controller on
board */
+ ide0_enable = "0";
+ ide1_enable = "0";
+};
--
coreboot mailing list
[email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
