On Thu, Oct 16, 2008 at 9:28 PM, Eric W. Biederman <[EMAIL PROTECTED]>wrote:
> Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
>
> > On 17.10.2008 02:50, Eric W. Biederman wrote:
> >> Carl-Daniel Hailfinger <[EMAIL PROTECTED]> writes:
> >>
> >>
> >>> I added a special case for ROMCC in the 0x...ULL constants in
> vt8237r.h.
> >>> Please see r3664.
> >>> The remaining segfault is being investigated by Eric.
> >>>
> >>
> >> It is reproducible, and it happens as the intermediate expression is
> being
> >> translated into intermediate code so it should be to weird to track.
> I'm
> >> going to guess 4-5 hours to sort through it. I will aim to look at it
> this
> >> weekend.
> >>
> >
> > Wow, that was unexpected. Thanks for investing your time!
>
> Yes. If the bug was down in the optimizer it would take to long to track.
>
> Eric
The break is caused by vt8237_early_spi_init(), most likely by spireg. Patch
to disable that function in ROMCC is attached, I know that via epia-cn,
pc2500, and jetway j7f2/4 don't use SPI, but I can't remember what the other
C7/CN700 board is right this moment to check. Thanks Carl-Daniel for fixing
the rest of vt8237, and Eric for your time :)
-Corey
Final fix for C7 boards, which are still using ROMCC, to be able to build. As
far as I know, no C7 boards currently in the tree use SPI flash.
Signed-off-by: Corey Osgood <[EMAIL PROTECTED]>
Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c (revision 3664)
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c (working copy)
@@ -336,6 +336,7 @@
pci_write_config8(dev, 0x41, 0x7f);
}
+#if defined(__GNUC__)
void vt8237_early_spi_init(void)
{
device_t dev;
@@ -358,6 +359,7 @@
spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c);
(*spireg) &= 0xff00;
}
+#endif
/* This #if is special. ROMCC chokes on the (rom == NULL) comparison.
* Since the whole function is only called for one target and that target
--
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