Author: myles
Date: 2008-11-05 23:27:36 +0100 (Wed, 05 Nov 2008)
New Revision: 983
Modified:
coreboot-v3/device/Makefile
coreboot-v3/device/cardbus_device.c
coreboot-v3/device/device.c
coreboot-v3/device/pci_device.c
coreboot-v3/device/pcie_device.c
coreboot-v3/include/device/cardbus.h
coreboot-v3/include/device/device.h
coreboot-v3/include/device/pci.h
coreboot-v3/include/device/pcie.h
Log:
This patch continues the device code cleanup.
The largest changes are to get_pci_bridge_ops, and related changes to make it
compile and use correct declarations.
While I was doing that I moved the checks for CONFIG_<BUS>_PLUGIN_SUPPORT to
the Makefile.
The only functional difference is a possible NULL dereference in a debug
statement.
I also added a few more consts, now that my other patch is in.
Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: coreboot-v3/device/Makefile
===================================================================
--- coreboot-v3/device/Makefile 2008-11-05 22:18:53 UTC (rev 982)
+++ coreboot-v3/device/Makefile 2008-11-05 22:27:36 UTC (rev 983)
@@ -29,13 +29,27 @@
smbus_ops.c
# this is only needed on the K8
+# This could also check for CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
ifeq ($(CONFIG_NORTHBRIDGE_AMD_K8),y)
STAGE2_DEVICE_SRC += hypertransport.c
endif
# this is only needed for pcix devices
+# This should also check for CONFIG_PCIX_PLUGIN_SUPPORT
ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y)
STAGE2_DEVICE_SRC += pcix_device.c
endif
+ifeq ($(CONFIG_PCIE_PLUGIN_SUPPORT),y)
+STAGE2_DEVICE_SRC += pcie_device.c
+endif
+
+ifeq ($(CONFIG_CARDBUS_PLUGIN_SUPPORT),y)
+STAGE2_DEVICE_SRC += cardbus_device.c
+endif
+
+ifeq ($(CONFIG_AGP_PLUGIN_SUPPORT),y)
+STAGE2_DEVICE_SRC += agp_device.c
+endif
+
$(obj)/device/pci_device.o: $(src)/device/pci_device.c $(obj)/statictree.h
Modified: coreboot-v3/device/cardbus_device.c
===================================================================
--- coreboot-v3/device/cardbus_device.c 2008-11-05 22:18:53 UTC (rev 982)
+++ coreboot-v3/device/cardbus_device.c 2008-11-05 22:27:36 UTC (rev 983)
@@ -94,7 +94,6 @@
resource_t moving_base, moving_limit, moving;
unsigned long type;
u16 ctl;
- unsigned long index;
/* See if needs a card control registers base address. */
@@ -243,11 +242,10 @@
}
const struct device_operations default_cardbus_ops_bus = {
- .read_resources = cardbus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = cardbus_enable_resources,
- .init = 0,
- .scan_bus = cardbus_scan_bridge,
- .enable = 0,
- .reset_bus = pci_bus_reset,
+ .phase3_scan = cardbus_scan_bridge,
+ .phase4_read_resources = cardbus_read_resources,
+ .phase4_set_resources = pci_dev_set_resources,
+ .phase5_enable_resources = cardbus_enable_resources,
+ .phase6_init = 0,
+ .reset_bus = pci_bus_reset,
};
Modified: coreboot-v3/device/device.c
===================================================================
--- coreboot-v3/device/device.c 2008-11-05 22:18:53 UTC (rev 982)
+++ coreboot-v3/device/device.c 2008-11-05 22:27:36 UTC (rev 983)
@@ -101,7 +101,7 @@
* @param dev Pointer to the newly created device structure.
* @param ops Pointer to device_operations
*/
-void default_device_constructor(struct device *dev, struct device_operations
*ops)
+void default_device_constructor(struct device *dev, const struct
device_operations *ops)
{
printk(BIOS_DEBUG, "default device constructor called\n");
dev->ops = ops;
@@ -146,7 +146,7 @@
void dev_init(void)
{
struct device *dev;
- struct device_operations *c;
+ const struct device_operations *c;
for (dev = all_devices; dev; dev = dev->next) {
c = dev->ops;
@@ -177,7 +177,7 @@
*/
void constructor(struct device *dev)
{
- struct device_operations *c;
+ const struct device_operations *c;
c = dev->ops;
Modified: coreboot-v3/device/pci_device.c
===================================================================
--- coreboot-v3/device/pci_device.c 2008-11-05 22:18:53 UTC (rev 982)
+++ coreboot-v3/device/pci_device.c 2008-11-05 22:27:36 UTC (rev 983)
@@ -30,28 +30,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-/* We should move these so they're really config options */
-#define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT 0
-#define CONFIG_PCIX_PLUGIN_SUPPORT 0
-#define CONFIG_PCIE_PLUGIN_SUPPORT 0
-#define CONFIG_CARDBUS_PLUGIN_SUPPORT 0
-#define CONFIG_AGP_PLUGIN_SUPPORT 0
-#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
-#include <device/hypertransport.h>
-#endif
-#if CONFIG_PCIX_PLUGIN_SUPPORT == 1
-#include <device/pcix.h>
-#endif
-#if CONFIG_PCIE_PLUGIN_SUPPORT == 1
-#include <device/pcie.h>
-#endif
-#if CONFIG_AGP_PLUGIN_SUPPORT == 1
-#include <device/agp.h>
-#endif
-#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
-#include <device/cardbus.h>
-#endif
#include <statictree.h>
u8 pci_moving_config8(struct device *dev, unsigned int reg)
@@ -759,11 +738,11 @@
}
/** Default device operation for PCI devices. */
-struct pci_operations pci_dev_ops_pci = {
+const struct pci_operations pci_dev_ops_pci = {
.set_subsystem = pci_dev_set_subsystem,
};
-struct device_operations default_pci_ops_dev = {
+const struct device_operations default_pci_ops_dev = {
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
@@ -773,11 +752,11 @@
};
/** Default device operations for PCI bridges. */
-struct pci_operations pci_bus_ops_pci = {
+const struct pci_operations pci_bus_ops_pci = {
.set_subsystem = 0,
};
-struct device_operations default_pci_ops_bus = {
+const struct device_operations default_pci_ops_bus = {
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
@@ -801,26 +780,28 @@
* @param dev Pointer to the device structure of the bridge.
* @return Appropriate bridge operations.
*/
-static struct device_operations *get_pci_bridge_ops(struct device *dev)
+static const struct device_operations *get_pci_bridge_ops(struct device *dev)
{
- // unsigned int pos;
-
-#if CONFIG_PCIX_PLUGIN_SUPPORT == 1
- pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
- if (pos) {
+#ifdef DEVICE_PCIX_H
+ unsigned int pcix_pos;
+ pcix_pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+ if (pcix_pos) {
printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n",
dev_path(dev));
return &default_pcix_ops_bus;
}
#endif
-#if CONFIG_AGP_PLUGIN_SUPPORT == 1
+#ifdef DEVICE_AGP_H
/* How do I detect an PCI to AGP bridge? */
+#warning AGP detection not implemented, so AGP bridge plugin not supported.
+
#endif
-#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
- pos = 0;
- while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
+#ifdef DEVICE_HYPERTRANSPORT_H
+ unsigned int ht_pos;
+ ht_pos = 0;
+ while ((ht_pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, ht_pos)))
{
unsigned int flags;
- flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
+ flags = pci_read_config16(dev, ht_pos + PCI_CAP_FLAGS);
if ((flags >> 13) == 1) {
/* Host or Secondary Interface. */
printk(BIOS_DEBUG,
@@ -830,11 +811,12 @@
}
}
#endif
-#if CONFIG_PCIE_PLUGIN_SUPPORT == 1
- pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
- if (pos) {
+#ifdef DEVICE_PCIE_H
+ unsigned int pcie_pos;
+ pcie_pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
+ if (pcie_pos) {
unsigned int flags;
- flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
+ flags = pci_read_config16(dev, pcie_pos + PCI_EXP_FLAGS);
switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
case PCI_EXP_TYPE_ROOT_PORT:
case PCI_EXP_TYPE_UPSTREAM:
@@ -864,7 +846,6 @@
static void set_pci_ops(struct device *dev)
{
struct device_operations *c;
- struct device_id id;
if (dev->ops) {
printk(BIOS_SPEW, "%s: dev %s already has ops of type %x\n",
@@ -872,8 +853,6 @@
return;
}
- id = dev->id;
-
/* Look through the list of setup drivers and find one for
* this PCI device.
*/
@@ -881,7 +860,7 @@
if (c) {
dev->ops = c;
printk(BIOS_SPEW, "%s id %s %sops\n",
- dev_path(dev), dev_id_string(&id),
+ dev_path(dev), dev_id_string(&dev->id),
(dev->ops->phase3_scan ? "bus " : ""));
return;
}
@@ -890,21 +869,30 @@
switch (dev->hdr_type & 0x7f) { /* Header type. */
case PCI_HEADER_TYPE_NORMAL: /* Standard header. */
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
- goto bad;
- dev->ops = &default_pci_ops_dev;
+ printk(BIOS_ERR,
+ "%s [%s] hdr_type %02x doesn't match"
+ "class %06x, ignoring.\n", dev_path(dev),
+ dev_id_string(&dev->id), dev->class >> 8,
+ dev->hdr_type);
+ else
+ dev->ops = &default_pci_ops_dev;
break;
case PCI_HEADER_TYPE_BRIDGE:
if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
- goto bad;
- dev->ops = get_pci_bridge_ops(dev);
+ printk(BIOS_ERR,
+ "%s [%s] hdr_type %02x doesn't match"
+ "class %06x, ignoring.\n", dev_path(dev),
+ dev_id_string(&dev->id), dev->class >> 8,
+ dev->hdr_type);
+ else
+ dev->ops = get_pci_bridge_ops(dev);
break;
-#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
+#ifdef DEVICE_CARDBUS_H
case PCI_HEADER_TYPE_CARDBUS:
dev->ops = &default_cardbus_ops_bus;
break;
#endif
default:
- bad:
if (dev->enabled) {
printk(BIOS_ERR,
"%s [%s/%06x] has unknown header "
@@ -914,7 +902,7 @@
}
}
printk(BIOS_INFO, "%s: dev %s set ops to type %x\n", __func__,
- dev->dtsname, dev->ops->id.type);
+ dev->dtsname, dev->ops? dev->ops->id.type : 0);
return;
}
Modified: coreboot-v3/device/pcie_device.c
===================================================================
--- coreboot-v3/device/pcie_device.c 2008-11-05 22:18:53 UTC (rev 982)
+++ coreboot-v3/device/pcie_device.c 2008-11-05 22:27:36 UTC (rev 983)
@@ -62,12 +62,11 @@
};
const struct device_operations default_pcie_ops_bus = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = 0,
- .scan_bus = pcie_scan_bridge,
- .enable = 0,
- .reset_bus = pci_bus_reset,
- .ops_pci = &pcie_bus_ops_pci,
+ .phase3_scan = pcie_scan_bridge,
+ .phase4_read_resources = pci_bus_read_resources,
+ .phase4_set_resources = pci_dev_set_resources,
+ .phase5_enable_resources = pci_bus_enable_resources,
+ .phase6_init = 0,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &pcie_bus_ops_pci,
};
Modified: coreboot-v3/include/device/cardbus.h
===================================================================
--- coreboot-v3/include/device/cardbus.h 2008-11-05 22:18:53 UTC (rev
982)
+++ coreboot-v3/include/device/cardbus.h 2008-11-05 22:27:36 UTC (rev
983)
@@ -27,6 +27,6 @@
unsigned int cardbus_scan_bridge(struct device *dev, unsigned int max);
void cardbus_enable_resources(struct device *dev);
-extern struct device_operations default_cardbus_ops_bus;
+extern const struct device_operations default_cardbus_ops_bus;
#endif /* DEVICE_CARDBUS_H */
Modified: coreboot-v3/include/device/device.h
===================================================================
--- coreboot-v3/include/device/device.h 2008-11-05 22:18:53 UTC (rev 982)
+++ coreboot-v3/include/device/device.h 2008-11-05 22:27:36 UTC (rev 983)
@@ -57,7 +57,6 @@
struct bus;
-
struct pci_domain_id
{
u16 vendor, device;
@@ -137,7 +136,7 @@
* constructors->constructor(constructors->constructor) and a new
* device is created.
*/
- void (*constructor)(struct device *, struct device_operations *);
+ void (*constructor)(struct device *, const struct device_operations *);
/* set device ops */
void (*phase1_set_device_operations)(struct device *dev);
@@ -231,7 +230,7 @@
/* number of buses attached to the device */
unsigned int links;
- struct device_operations *ops;
+ const struct device_operations *ops;
void *device_configuration;
};
@@ -273,7 +272,7 @@
struct device * dev_find_slot (unsigned int bus, unsigned int devfn);
EXPORT_SYMBOL(dev_find_slot);
struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr);
-void default_device_constructor(struct device *dev, struct device_operations
*constructor);
+void default_device_constructor(struct device *dev, const struct
device_operations *constructor);
/* Rounding for boundaries.
Modified: coreboot-v3/include/device/pci.h
===================================================================
--- coreboot-v3/include/device/pci.h 2008-11-05 22:18:53 UTC (rev 982)
+++ coreboot-v3/include/device/pci.h 2008-11-05 22:27:36 UTC (rev 983)
@@ -71,10 +71,10 @@
extern struct pci_driver epci_drivers[];
-extern struct device_operations default_pci_ops_dev;
-extern struct device_operations default_pci_ops_bus;
-extern struct pci_operations pci_dev_ops_pci;
-extern struct pci_operations pci_bus_ops_pci;
+extern const struct device_operations default_pci_ops_dev;
+extern const struct device_operations default_pci_ops_bus;
+extern const struct pci_operations pci_dev_ops_pci;
+extern const struct pci_operations pci_bus_ops_pci;
void pci_dev_read_resources(struct device * dev);
void pci_bus_read_resources(struct device * dev);
Modified: coreboot-v3/include/device/pcie.h
===================================================================
--- coreboot-v3/include/device/pcie.h 2008-11-05 22:18:53 UTC (rev 982)
+++ coreboot-v3/include/device/pcie.h 2008-11-05 22:27:36 UTC (rev 983)
@@ -26,6 +26,6 @@
unsigned min_devfn, unsigned max_devfn, unsigned int max);
unsigned int pcie_scan_bridge(struct device *dev, unsigned int max);
-extern struct device_operations default_pcie_ops_bus;
+extern const struct device_operations default_pcie_ops_bus;
#endif /* DEVICE_PCIE_H */
--
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