Hi, My Athlon64 / K8 socket 939 setup needed the following adjustments to fix memory read/write errors. Thanks to Rudolf for hinting on which bits I should check for. Details:
- bit 9, mandated by spec to always be set on sodimm or socket 939 dual dimm. - bit 28, enable 2T timing. no idea why, but I get memory errors without it. - bit 29, upper chip select. mandated by spec on socket 939. My patch also adds missing descriptions, based on the ones from the spec (http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.pdf) -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."
Signed-off-by: Robert Millan <[EMAIL PROTECTED]> Index: src/northbridge/amd/amdk8/raminit.c =================================================================== --- src/northbridge/amd/amdk8/raminit.c (revision 3761) +++ src/northbridge/amd/amdk8/raminit.c (working copy) @@ -344,9 +344,9 @@ static void sdram_set_registers(const st * [ 8: 8] DRAM_Init * 0 = Initialization done or not yet started. * 1 = Initiate DRAM intialization sequence - * [ 9: 9] SO-Dimm Enable + * [ 9: 9] Dual Dimm Enable * 0 = Do nothing - * 1 = SO-Dimms present + * 1 = Dual-Dimms present (needed for either SO-DIMM or socket 939) * [10:10] DramEnable * 0 = DRAM not enabled * 1 = DRAM initialized and enabled @@ -394,14 +394,26 @@ static void sdram_set_registers(const st * 101 = Oldest entry in DCQ can be bypassed 5 times * 110 = Oldest entry in DCQ can be bypassed 6 times * 111 = Oldest entry in DCQ can be bypassed 7 times - * [31:28] Reserved + * [28:28] Enable 2T timing + * 0 = 2T timing disabled + * 1 = 2T timing enabled + * [29:29] Upper chip select mapping + * 0 = CS map disabled + * 1 = CS map enabled (must be set on socket 939) + * [31:30] Power Down Control + * 00 = Power down disabled + * 01 = Alternating DIMM clock enable control + * 10 = Same DIMM clock enable control + * 11 = Independent DIMM clock enable control */ - PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, + PCI_ADDR(0, 0x18, 2, 0x90), 0xc0000000, + (1 << 29)| + (1 << 28)| (4 << 25)|(0 << 24)| (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| (1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| (2 << 14)|(0 << 13)|(0 << 12)| - (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| + (0 << 11)|(0 << 10)|(1 << 9)|(0 << 8)| (0 << 3) |(0 << 1) |(0 << 0), /* DRAM Config High Register * F2:0x94
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