On Wed, Nov 19, 2008 at 03:32:26PM -0800, ron minnich wrote: > On Wed, Nov 19, 2008 at 3:01 PM, Robert Millan <[EMAIL PROTECTED]> wrote: > > > > Hi, > > > > My Athlon64 / K8 socket 939 setup needed the following adjustments to fix > > memory read/write errors. Thanks to Rudolf for hinting on which bits I > > should check for. Details: > > > > - bit 9, mandated by spec to always be set on sodimm or socket 939 dual > > dimm. > > > > - bit 28, enable 2T timing. no idea why, but I get memory errors without > > it. > > > > - bit 29, upper chip select. mandated by spec on socket 939. > > > > My patch also adds missing descriptions, based on the ones from the spec > > (http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.pdf) > > > > Given that these settings are mainboard and socket dependent, we need > a way to do these settings that takes those factors into account. > > It seems to me that setting 2T on very athlon64 platform is not the > way to do it. > > Thanks for finding this and getting us this initial patch. Do you > think you can extend it in some way so we don't slow down all k8 > platforms?
Okay. Bit 29 is the easiest, as the spec reads "This bit should be set if the 939 package is used." This is enough for a single-DIMM setup to work. -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."
Signed-off-by: Robert Millan <[EMAIL PROTECTED]> Index: src/cpu/amd/socket_939/Config.lb =================================================================== --- src/cpu/amd/socket_939/Config.lb (revision 3761) +++ src/cpu/amd/socket_939/Config.lb (working copy) @@ -1,9 +1,12 @@ uses CONFIG_CHIP_NAME +uses CPU_SOCKET_TYPE if CONFIG_CHIP_NAME config chip.h end +default CPU_SOCKET_TYPE=0x13 + object socket_939.o dir /cpu/amd/model_fxx Index: src/northbridge/amd/amdk8/raminit.c =================================================================== --- src/northbridge/amd/amdk8/raminit.c (revision 3761) +++ src/northbridge/amd/amdk8/raminit.c (working copy) @@ -394,9 +394,22 @@ static void sdram_set_registers(const st * 101 = Oldest entry in DCQ can be bypassed 5 times * 110 = Oldest entry in DCQ can be bypassed 6 times * 111 = Oldest entry in DCQ can be bypassed 7 times - * [31:28] Reserved + * [28:28] Enable 2T timing + * 0 = 2T timing disabled + * 1 = 2T timing enabled + * [29:29] Upper chip select mapping + * 0 = CS map disabled + * 1 = CS map enabled + * [31:30] Power Down Control + * 00 = Power down disabled + * 01 = Alternating DIMM clock enable control + * 10 = Same DIMM clock enable control + * 11 = Independent DIMM clock enable control */ - PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, + PCI_ADDR(0, 0x18, 2, 0x90), 0xc0000000, +#if CPU_SOCKET_TYPE == 0x13 /* Socket 939 */ + (1 << 29)| +#endif (4 << 25)|(0 << 24)| (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| (1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)|
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