-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hello,
I obtained some SAS PCIe card. I have some good and bad news ;)
1) it does not work at all, PCI ROM signature wrong.
2) it does work with some help glitch
3) it does not work as expected
I solved 1) with a simple hack patch (attached) The PCI ROM BARs should not be
relocated. The K8 processor has some PCI hole resource and imho there is a
problem that even the PCI hole starts at TOPMEM, it still hits RAM because of
video framebuffer for integrated VGA.
I fixed this isssue by not touching PCI ROM base, check the patch.
2) It does work! PCI option rom get executed. This particular ROM has "press
space to skip" option, and if I do that I get to grub/linux whatever.
3) If I do not press space, the PCI option rom is supposed to init the HW.
it just freezes somewhere inside, but keyboard IRQ still delivered.
With original BIOS, some other screen is printed with another screen mode, but
it freezes too ;)))
Some remark to the end. I'm not sure if next_rom pointer should be adjusted
before the rom is copied.
In my case VGA has someting like 36KB and with 2K align it gets to 0xCA000 for
next ROM. I tried with ALIGN of 64KB but it does not help that particular silly
option rom :) Maybe the align should be handled also depending on actual rom
size. I mean "allow spaces for aligns between roms".
Rudolf
Here are some debug messages:
Attempting to find coreboot table
Copying ACPI RSDP from 1bff0000 to 000ff330
init SMBIOS tables
Found 1 cpu(s)
SMBIOS table addr=0x000ff350
ram_size=0x1bff0000
Scan for VGA option rom
Attempting to init PCI bdf 00000100
Copying option rom from fff80000 (ROM) to 000c0000 (RAM)
Running option rom at 0000c000:00000003
fail handle_155fXX:47(00000086):
a=00005f18 b=000002e4 c=00000000 d=000003c3 si=00000000 di=0000e261
ds=00000000 es=0000f000 ip=00008c26 cs=0000c000 f=00000006 r=00007926
Turning on vga console
Starting SeaBIOS
...
...
Attempting to map option rom on dev 000000c3
Option rom sizing returned 00000000 00000000
Attempting to init PCI bdf 00000200
Attempting to map option rom on dev 00000200
Option rom sizing returned f1100000 fffc0000
Card 00000200 option rom mapped at f1100000
Copying option rom from f1100000 (ROM) to 000d0000 (RAM)
Running option rom at 0000d000:00000003
Changing serial settings was 00000003/00000002 now 00000003/00000000
Attempting to init PCI bdf 00000408
Attempting to map option rom on dev 00000408
Option rom sizing returned 00000000 00000000
Press F12 for boot menu.
Some example of PCI/MEMORY resources, from another computer via the k8resdump
(check Coreboot util)
DRAM map: #0 0x0000000000 - 0x003fffffff Access: R/W IntlvEN:0x0 IntlvSEL:0x0
Dstnode:0
DRAM map: #1 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0
Dstnode:1
DRAM map: #2 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0
Dstnode:2
DRAM map: #3 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0
Dstnode:3
DRAM map: #4 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0
Dstnode:4
DRAM map: #5 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0
Dstnode:5
DRAM map: #6 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0
Dstnode:6
DRAM map: #7 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0
Dstnode:7
MMIO map: #0 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
MMIO map: #1 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
MMIO map: #2 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
MMIO map: #3 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
MMIO map: #4 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
MMIO map: #5 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0
MMIO map: #6 0x00000a0000 - 0x00000bffff Access: R/W Dstnode:0 DstLink 0
MMIO map: #7 0x0040000000 - 0x00ff70ffff Access: R/W Dstnode:0 DstLink 0
IO map: #0 0x000000 - 0x000fff Access: / Dstnode:0 DstLink 0
IO map: #1 0x001000 - 0x0fffff Access: R/W VGA Dstnode:0 DstLink 0
IO map: #2 0x000000 - 0x000fff Access: / Dstnode:0 DstLink 0
IO map: #3 0x000000 - 0x000fff Access: / Dstnode:0 DstLink 0
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iEYEARECAAYFAkkrNaEACgkQ3J9wPJqZRNWa6gCeLV7DszkrcuNR0vGzzZs9GW7H
ALQAmgKV18+HnsAGgmRNiKM3enmYT6Xe
=PXog
-----END PGP SIGNATURE-----
diff --git a/src/config.h b/src/config.h
index 1a22cd8..886d93f 100644
--- a/src/config.h
+++ b/src/config.h
@@ -13,13 +13,13 @@
#define CONFIG_APPNAME4 "BXPC"
// Configure as a coreboot payload.
-#define CONFIG_COREBOOT 0
+#define CONFIG_COREBOOT 1
// Control how verbose debug output is.
-#define CONFIG_DEBUG_LEVEL 1
+#define CONFIG_DEBUG_LEVEL 6
// Send debugging information to serial port
-#define CONFIG_DEBUG_SERIAL 0
+#define CONFIG_DEBUG_SERIAL 1
// Support for int13 floppy drive access
#define CONFIG_FLOPPY_SUPPORT 1
@@ -48,7 +48,7 @@
// Support finding and running option roms during post.
#define CONFIG_OPTIONROMS 1
// Set if option roms are already copied to 0xc0000-0xf0000
-#define CONFIG_OPTIONROMS_DEPLOYED 1
+#define CONFIG_OPTIONROMS_DEPLOYED 0
// Support an interactive boot menu at end of post.
#define CONFIG_BOOTMENU 1
diff --git a/src/optionroms.c b/src/optionroms.c
index 1c1b791..8053646 100644
--- a/src/optionroms.c
+++ b/src/optionroms.c
@@ -65,14 +65,15 @@ struct pnp_data {
u16 staticresource;
} PACKED;
-#define OPTIONROM_BDF_1 0x0000
-#define OPTIONROM_MEM_1 0x00000000
+#define OPTIONROM_BDF_1 0x0100
+#define OPTIONROM_MEM_1 0xfff80000
+
#define OPTIONROM_BDF_2 0x0000
#define OPTIONROM_MEM_2 0x00000000
#define OPTION_ROM_START 0xc0000
#define OPTION_ROM_SIGNATURE 0xaa55
-#define OPTION_ROM_ALIGN 2048
+#define OPTION_ROM_ALIGN (0xffff + 1)
#define OPTION_ROM_INITVECTOR offsetof(struct rom_header, initVector[0])
// Next available position for an option rom.
@@ -186,11 +187,13 @@ map_optionrom(u16 bdf)
if (!sz || sz == 0xffffffff)
goto fail;
+ pci_config_writel(bdf, PCI_ROM_ADDRESS, orig | PCI_ROM_ADDRESS_ENABLE);
+
// Looks like a rom - map it to just above end of memory.
- u32 mappos = ALIGN(GET_EBDA(ram_size), OPTION_ROM_ALIGN);
- pci_config_writel(bdf, PCI_ROM_ADDRESS, mappos | PCI_ROM_ADDRESS_ENABLE);
+// u32 mappos = ALIGN(GET_EBDA(ram_size), OPTION_ROM_ALIGN);
+ // pci_config_writel(bdf, PCI_ROM_ADDRESS, mappos | PCI_ROM_ADDRESS_ENABLE);
- struct rom_header *rom = (struct rom_header *)mappos;
+ struct rom_header *rom = (struct rom_header *) orig;
if (rom->signature != OPTION_ROM_SIGNATURE) {
dprintf(6, "No option rom signature (got %x)\n", rom->signature);
goto fail;
@@ -223,9 +226,9 @@ init_optionrom(u16 bdf)
pci_config_writel(bdf, PCI_ROM_ADDRESS, next_rom);
return NULL;
}
- dprintf(4, "Copying option rom from %p to %x\n", rom, next_rom);
+ dprintf(4, "Copying option rom from %p (ROM) to %x (RAM)\n", rom, next_rom);
memcpy((void*)next_rom, rom, romsize);
- pci_config_writel(bdf, PCI_ROM_ADDRESS, next_rom);
+// pci_config_writel(bdf, PCI_ROM_ADDRESS, next_rom);
rom = (struct rom_header *)next_rom;
if (! is_valid_rom(rom))
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
