Thanks. Does coreboot setup the option rom bar with a valid value?
Yes it does.
If so, this makes things easy - I can just enable the existing value.
I think it may be enabled. Linux will disable the BAR.
here is a tip how to read option rom in linux:
cd /sys/bus/pci/devices/0000\:02\:00.0
echo enable > rom
hexdump -C rom
Note that your patch doesn't seem to disable the mapping after the
copy. This is definitely necessary. Maybe add something like:
pci_config_writel(bdf, PCI_ROM_ADDRESS, orig & ~PCI_ROM_ADDRESS_ENABLE);
Why we need it to disable? Just curious. Coreboot has assigned the address to it
so we are sure we won't be hit by something else.
Also, since the initial SeaBIOS support, I found the pci spec (google
for "PCI Firmware Specification v3.0 (2005-06-20).pdf"), and it
indicates that multiple firmware images can be in the rom - the BIOS
needs to walk the list and find the right one depending on the PCI
headers. Sigh - this stuff's never simple.
Yep ok.
As near as I can tell, the code that updates next_rom is correct. We
don't want to increase next_rom until after the pnp init function is
called, because that function can resize the rom.
OK the behavior did not change anyway.
I can try to test with mine PCIe SATA card. Do you think it will correctly patch
the BIOS so I will be at the end able to boot from it?
Rudolf
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
