Hi guys
I don't know how usefull is it but there is a bug in cache_as_ram.inc
and cache_as_ram_post.c for the 6fx intel processors. The code disable /
enable the prefetcher in IA32_MISC_ENABLES MSR register.
cache_as_ram.inc :
/* Disable prefetchers */
movl $0x01a0, %eax
rdmsr
orl $((1 << 9) | (1 << 19)), %eax
orl $((1 << 5) | (1 << 7)), %edx
wrmsr
should be
movl $0x01a0, %ecx
Same thing in cache_as_ram_post.c
/* Enable prefetchers */
"movl $0x01a0, %eax\n"
"rdmsr\n"
"andl $~((1 << 9) | (1 << 19)), %eax\n"
"andl $~((1 << 5) | (1 << 7)), %edx\n"
"wrmsr\n"
should be
"movl $0x01a0, %ecx\n"
Regards,
Thomas
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