On 05.12.2008 09:53, Corey Osgood wrote: > On Wed, Dec 3, 2008 at 5:27 PM, ron minnich <[EMAIL PROTECTED]> wrote: > >> In fact, if anything, can we please fix the cn700? >> > > Working on it! > > Current status: a GPIO line isn't getting disabled for some reason (even > though it's disabled several times), and the damn chipset reboots when the > timer it controls expires. Once the board reboots, something isn't working > correctly, presumably CAR, and the LAR can't be read from. I'm working from > revision 1010, but I think it's the same status in current svn. I'll be > spending more time with it this weekend, from the sound of the weather > report I won't be able to do much else anyways :p >
Could you give me a little more verbose info? If CAR is not working, printk should not work (or at least crash directly after the first call). Having the ROM not mapped also looks weird. I don't doubt your description, I'm just trying to understand it. In theory, the different cache behaviour of the C7 on poweron could be related... can you try issuing a reset from inside coreboot and check if the same problem appears after your deliberate reset? Oh, and please check how the processor behaves if you press the reset button. I hope to find a pattern here. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
